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authorTsiChung Liew <Tsi-Chung.Liew@freescale.com>2008-10-21 10:03:07 +0000
committerJohn Rigby <jrigby@freescale.com>2008-11-03 09:45:58 -0700
commit012522fef3b382469125beb46a315ab4dee02fb0 (patch)
tree9bc6b0cc47ec08dd3efb07a75eaa50fd04ec5f32 /include/asm-m68k/immap_5227x.h
parentac2331aee99ad36be0fcfed8c49922e3c61b576d (diff)
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ColdFire: Modules header files cleanup
Consolidate ATA, ePORT, QSPI, FlexCan, PWM, RNG, MDHA, SKHA, INTC, and FlexBus structures and definitions in immap_5xxx.h to more unify modules header files. Append DSPI support for m547x_8x. SSI cleanup. Remove USB Host structure from immap_539.h. Apply changes to use FlexBus structures in mcf52x2's cpu_init.c and platform configuration files. Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
Diffstat (limited to 'include/asm-m68k/immap_5227x.h')
-rw-r--r--include/asm-m68k/immap_5227x.h109
1 files changed, 10 insertions, 99 deletions
diff --git a/include/asm-m68k/immap_5227x.h b/include/asm-m68k/immap_5227x.h
index 83da3d5..6f65f50 100644
--- a/include/asm-m68k/immap_5227x.h
+++ b/include/asm-m68k/immap_5227x.h
@@ -69,109 +69,14 @@
#include <asm/coldfire/crossbar.h>
#include <asm/coldfire/dspi.h>
#include <asm/coldfire/edma.h>
+#include <asm/coldfire/eport.h>
#include <asm/coldfire/flexbus.h>
+#include <asm/coldfire/flexcan.h>
+#include <asm/coldfire/intctrl.h>
#include <asm/coldfire/lcd.h>
+#include <asm/coldfire/pwm.h>
#include <asm/coldfire/ssi.h>
-/* Interrupt Controller (INTC) */
-typedef struct int0_ctrl {
- u32 iprh0; /* 0x00 Pending Register High */
- u32 iprl0; /* 0x04 Pending Register Low */
- u32 imrh0; /* 0x08 Mask Register High */
- u32 imrl0; /* 0x0C Mask Register Low */
- u32 frch0; /* 0x10 Force Register High */
- u32 frcl0; /* 0x14 Force Register Low */
- u16 res1; /* 0x18 - 0x19 */
- u16 icfg0; /* 0x1A Configuration Register */
- u8 simr0; /* 0x1C Set Interrupt Mask */
- u8 cimr0; /* 0x1D Clear Interrupt Mask */
- u8 clmask0; /* 0x1E Current Level Mask */
- u8 slmask; /* 0x1F Saved Level Mask */
- u32 res2[8]; /* 0x20 - 0x3F */
- u8 icr0[64]; /* 0x40 - 0x7F Control registers */
- u32 res3[24]; /* 0x80 - 0xDF */
- u8 swiack0; /* 0xE0 Software Interrupt ack */
- u8 res4[3]; /* 0xE1 - 0xE3 */
- u8 Lniack0_1; /* 0xE4 Level n interrupt ack */
- u8 res5[3]; /* 0xE5 - 0xE7 */
- u8 Lniack0_2; /* 0xE8 Level n interrupt ack */
- u8 res6[3]; /* 0xE9 - 0xEB */
- u8 Lniack0_3; /* 0xEC Level n interrupt ack */
- u8 res7[3]; /* 0xED - 0xEF */
- u8 Lniack0_4; /* 0xF0 Level n interrupt ack */
- u8 res8[3]; /* 0xF1 - 0xF3 */
- u8 Lniack0_5; /* 0xF4 Level n interrupt ack */
- u8 res9[3]; /* 0xF5 - 0xF7 */
- u8 Lniack0_6; /* 0xF8 Level n interrupt ack */
- u8 resa[3]; /* 0xF9 - 0xFB */
- u8 Lniack0_7; /* 0xFC Level n interrupt ack */
- u8 resb[3]; /* 0xFD - 0xFF */
-} int0_t;
-
-typedef struct int1_ctrl {
- /* Interrupt Controller 1 */
- u32 iprh1; /* 0x00 Pending Register High */
- u32 iprl1; /* 0x04 Pending Register Low */
- u32 imrh1; /* 0x08 Mask Register High */
- u32 imrl1; /* 0x0C Mask Register Low */
- u32 frch1; /* 0x10 Force Register High */
- u32 frcl1; /* 0x14 Force Register Low */
- u16 res1; /* 0x18 */
- u16 icfg1; /* 0x1A Configuration Register */
- u8 simr1; /* 0x1C Set Interrupt Mask */
- u8 cimr1; /* 0x1D Clear Interrupt Mask */
- u16 res2; /* 0x1E - 0x1F */
- u32 res3[8]; /* 0x20 - 0x3F */
- u8 icr1[64]; /* 0x40 - 0x7F */
- u32 res4[24]; /* 0x80 - 0xDF */
- u8 swiack1; /* 0xE0 Software Interrupt ack */
- u8 res5[3]; /* 0xE1 - 0xE3 */
- u8 Lniack1_1; /* 0xE4 Level n interrupt ack */
- u8 res6[3]; /* 0xE5 - 0xE7 */
- u8 Lniack1_2; /* 0xE8 Level n interrupt ack */
- u8 res7[3]; /* 0xE9 - 0xEB */
- u8 Lniack1_3; /* 0xEC Level n interrupt ack */
- u8 res8[3]; /* 0xED - 0xEF */
- u8 Lniack1_4; /* 0xF0 Level n interrupt ack */
- u8 res9[3]; /* 0xF1 - 0xF3 */
- u8 Lniack1_5; /* 0xF4 Level n interrupt ack */
- u8 resa[3]; /* 0xF5 - 0xF7 */
- u8 Lniack1_6; /* 0xF8 Level n interrupt ack */
- u8 resb[3]; /* 0xF9 - 0xFB */
- u8 Lniack1_7; /* 0xFC Level n interrupt ack */
- u8 resc[3]; /* 0xFD - 0xFF */
-} int1_t;
-
-/* Global Interrupt Acknowledge (IACK) */
-typedef struct iack {
- u8 resv0[0xE0];
- u8 gswiack;
- u8 resv1[0x3];
- u8 gl1iack;
- u8 resv2[0x3];
- u8 gl2iack;
- u8 resv3[0x3];
- u8 gl3iack;
- u8 resv4[0x3];
- u8 gl4iack;
- u8 resv5[0x3];
- u8 gl5iack;
- u8 resv6[0x3];
- u8 gl6iack;
- u8 resv7[0x3];
- u8 gl7iack;
-} iack_t;
-
-/* Edge Port Module (EPORT) */
-typedef struct eport {
- u16 eppar;
- u8 epddr;
- u8 epier;
- u8 epdr;
- u8 eppdr;
- u8 epfr;
-} eport_t;
-
/* Reset Controller Module (RCM) */
typedef struct rcm {
u8 rcr;
@@ -193,6 +98,12 @@ typedef struct ccm {
u16 sbfcr; /* Serial Boot Control */
} ccm_t;
+typedef struct canex_ctrl {
+ can_msg_t msg[16]; /* 0x00 Message Buffer 0-15 */
+ u32 res0[0x700]; /* 0x100 */
+ can_msg_t rxim[16]; /* 0x800 Rx Individual Mask 0-15 */
+} canex_t;
+
/* General Purpose I/O Module (GPIO) */
typedef struct gpio {
/* Port Output Data Registers */