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| author | Stefan Roese <sr@denx.de> | 2007-03-31 13:44:12 +0200 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2007-03-31 13:44:12 +0200 |
| commit | 0e7d4916afaf83083b9b70ad779f29f7b57bd8ed (patch) | |
| tree | 40e9396ee819149a89f520f551d1ed31cb8f5216 /include/asm-blackfin/mem_init.h | |
| parent | da6ebc1bc082cbe3b6bbde079cafe09f7ebbad4b (diff) | |
| parent | 6db7d0af2336c126e4d4b2f248cc23516bdd46a8 (diff) | |
| download | u-boot-imx-0e7d4916afaf83083b9b70ad779f29f7b57bd8ed.zip u-boot-imx-0e7d4916afaf83083b9b70ad779f29f7b57bd8ed.tar.gz u-boot-imx-0e7d4916afaf83083b9b70ad779f29f7b57bd8ed.tar.bz2 | |
Merge with git://www.denx.de/git/u-boot.git
Diffstat (limited to 'include/asm-blackfin/mem_init.h')
| -rw-r--r-- | include/asm-blackfin/mem_init.h | 46 |
1 files changed, 40 insertions, 6 deletions
diff --git a/include/asm-blackfin/mem_init.h b/include/asm-blackfin/mem_init.h index 1a13d90..d9d8bf9 100644 --- a/include/asm-blackfin/mem_init.h +++ b/include/asm-blackfin/mem_init.h @@ -22,7 +22,13 @@ * MA 02111-1307 USA */ -#if ( CONFIG_MEM_MT48LC16M16A2TG_75 || CONFIG_MEM_MT48LC64M4A2FB_7E ) +#if (CONFIG_MEM_MT48LC16M16A2TG_75 || \ + CONFIG_MEM_MT48LC64M4A2FB_7E || \ + CONFIG_MEM_MT48LC16M8A2TG_75 || \ + CONFIG_MEM_MT48LC8M16A2TG_7E || \ + CONFIG_MEM_MT48LC8M32B2B5_7 || \ + CONFIG_MEM_MT48LC32M8A2_75) + #if ( CONFIG_SCLK_HZ > 119402985 ) #define SDRAM_tRP TRP_2 #define SDRAM_tRP_num 2 @@ -66,7 +72,7 @@ #if ( CONFIG_SCLK_HZ > 59701493 ) && ( CONFIG_SCLK_HZ <= 66666667 ) #define SDRAM_tRP TRP_1 #define SDRAM_tRP_num 1 - #define SDRAM_tRAS TRAS_4 + #define SDRAM_tRAS TRAS_3 #define SDRAM_tRAS_num 3 #define SDRAM_tRCD TRCD_1 #define SDRAM_tWR TWR_2 @@ -99,18 +105,46 @@ #if (CONFIG_MEM_MT48LC16M16A2TG_75) /*SDRAM INFORMATION: */ - #define SDRAM_Tref 64 /* Refresh period in milliseconds */ - #define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */ + #define SDRAM_Tref 64 /* Refresh period in milliseconds */ + #define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */ #define SDRAM_CL CL_3 #endif #if (CONFIG_MEM_MT48LC64M4A2FB_7E) /*SDRAM INFORMATION: */ - #define SDRAM_Tref 64 /* Refresh period in milliseconds */ - #define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */ + #define SDRAM_Tref 64 /* Refresh period in milliseconds */ + #define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */ + #define SDRAM_CL CL_2 +#endif + +#if (CONFIG_MEM_MT48LC16M8A2TG_75) + /*SDRAM INFORMATION: */ + #define SDRAM_Tref 64 /* Refresh period in milliseconds */ + #define SDRAM_NRA 4096 /* Number of row addresses in SDRAM */ + #define SDRAM_CL CL_3 +#endif + +#if (CONFIG_MEM_MT48LC32M8A2_75) +/*SDRAM INFORMATION: */ +#define SDRAM_Tref 64 /* Refresh period in milliseconds */ +#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */ +#define SDRAM_CL CL_3 +#endif + +#if (CONFIG_MEM_MT48LC8M16A2TG_7E) + /*SDRAM INFORMATION: */ + #define SDRAM_Tref 64 /* Refresh period in milliseconds */ + #define SDRAM_NRA 4096 /* Number of row addresses in SDRAM */ #define SDRAM_CL CL_2 #endif +#if (CONFIG_MEM_MT48LC8M32B2B5_7) + /*SDRAM INFORMATION: */ + #define SDRAM_Tref 64 /* Refresh period in milliseconds */ + #define SDRAM_NRA 4096 /* Number of row addresses in SDRAM */ + #define SDRAM_CL CL_3 +#endif + #if ( CONFIG_MEM_SIZE == 128 ) #define SDRAM_SIZE EBSZ_128 #endif |