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authorWolfgang Denk <wd@denx.de>2009-03-25 22:43:25 +0100
committerWolfgang Denk <wd@denx.de>2009-03-25 22:43:25 +0100
commit2c5bd16af132bb6e9158c43fc6206fa0f1f501c1 (patch)
tree39c3dd1da3692cbe609f66f4d004451944d89771 /include/asm-blackfin/mach-bf561
parent196c74311f394c6eb08bd9ab07a35671299b9851 (diff)
parent4de1a5daab079ddc8ce1274144700203d692105c (diff)
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Merge branch 'master' of git://git.denx.de/u-boot-blackfin
Diffstat (limited to 'include/asm-blackfin/mach-bf561')
-rw-r--r--include/asm-blackfin/mach-bf561/BF561_cdef.h12
-rw-r--r--include/asm-blackfin/mach-bf561/anomaly.h7
-rw-r--r--include/asm-blackfin/mach-bf561/def_local.h2
-rw-r--r--include/asm-blackfin/mach-bf561/ports.h44
4 files changed, 57 insertions, 8 deletions
diff --git a/include/asm-blackfin/mach-bf561/BF561_cdef.h b/include/asm-blackfin/mach-bf561/BF561_cdef.h
index d8883f3..e2c165a 100644
--- a/include/asm-blackfin/mach-bf561/BF561_cdef.h
+++ b/include/asm-blackfin/mach-bf561/BF561_cdef.h
@@ -244,9 +244,9 @@
#define pSICA_SWRST ((uint16_t volatile *)SICA_SWRST)
#define bfin_read_SICA_SWRST() bfin_read16(SICA_SWRST)
#define bfin_write_SICA_SWRST(val) bfin_write16(SICA_SWRST, val)
-#define pSICA_SYSCR ((uint32_t volatile *)SICA_SYSCR)
-#define bfin_read_SICA_SYSCR() bfin_read32(SICA_SYSCR)
-#define bfin_write_SICA_SYSCR(val) bfin_write32(SICA_SYSCR, val)
+#define pSICA_SYSCR ((uint16_t volatile *)SICA_SYSCR)
+#define bfin_read_SICA_SYSCR() bfin_read16(SICA_SYSCR)
+#define bfin_write_SICA_SYSCR(val) bfin_write16(SICA_SYSCR, val)
#define pSICA_RVECT ((uint16_t volatile *)SICA_RVECT)
#define bfin_read_SICA_RVECT() bfin_read16(SICA_RVECT)
#define bfin_write_SICA_RVECT(val) bfin_write16(SICA_RVECT, val)
@@ -295,9 +295,9 @@
#define pSICB_SWRST ((uint16_t volatile *)SICB_SWRST)
#define bfin_read_SICB_SWRST() bfin_read16(SICB_SWRST)
#define bfin_write_SICB_SWRST(val) bfin_write16(SICB_SWRST, val)
-#define pSICB_SYSCR ((uint32_t volatile *)SICB_SYSCR)
-#define bfin_read_SICB_SYSCR() bfin_read32(SICB_SYSCR)
-#define bfin_write_SICB_SYSCR(val) bfin_write32(SICB_SYSCR, val)
+#define pSICB_SYSCR ((uint16_t volatile *)SICB_SYSCR)
+#define bfin_read_SICB_SYSCR() bfin_read16(SICB_SYSCR)
+#define bfin_write_SICB_SYSCR(val) bfin_write16(SICB_SYSCR, val)
#define pSICB_RVECT ((uint16_t volatile *)SICB_RVECT)
#define bfin_read_SICB_RVECT() bfin_read16(SICB_RVECT)
#define bfin_write_SICB_RVECT(val) bfin_write16(SICB_RVECT, val)
diff --git a/include/asm-blackfin/mach-bf561/anomaly.h b/include/asm-blackfin/mach-bf561/anomaly.h
index 1a9e175..d0b0b35 100644
--- a/include/asm-blackfin/mach-bf561/anomaly.h
+++ b/include/asm-blackfin/mach-bf561/anomaly.h
@@ -2,7 +2,7 @@
* File: include/asm-blackfin/mach-bf561/anomaly.h
* Bugs: Enter bugs at http://blackfin.uclinux.org/
*
- * Copyright (C) 2004-2008 Analog Devices Inc.
+ * Copyright (C) 2004-2009 Analog Devices Inc.
* Licensed under the GPL-2 or later.
*/
@@ -224,7 +224,7 @@
#define ANOMALY_05000301 (1)
/* SSYNCs After Writes To DMA MMR Registers May Not Be Handled Correctly */
#define ANOMALY_05000302 (1)
-/* New Feature: Additional Hysteresis on SPORT Input Pins (Not Available On Older Silicon) */
+/* SPORT_HYS Bit in PLL_CTL Register Is Not Functional */
#define ANOMALY_05000305 (__SILICON_REVISION__ < 5)
/* SCKELOW Bit Does Not Maintain State Through Hibernate */
#define ANOMALY_05000307 (__SILICON_REVISION__ < 5)
@@ -283,8 +283,11 @@
#define ANOMALY_05000273 (0)
#define ANOMALY_05000311 (0)
#define ANOMALY_05000353 (1)
+#define ANOMALY_05000380 (0)
#define ANOMALY_05000386 (1)
#define ANOMALY_05000432 (0)
#define ANOMALY_05000435 (0)
+#define ANOMALY_05000447 (0)
+#define ANOMALY_05000448 (0)
#endif
diff --git a/include/asm-blackfin/mach-bf561/def_local.h b/include/asm-blackfin/mach-bf561/def_local.h
index 3ddd689..597dcec 100644
--- a/include/asm-blackfin/mach-bf561/def_local.h
+++ b/include/asm-blackfin/mach-bf561/def_local.h
@@ -8,3 +8,5 @@
#define bfin_write_WDOG_CNT(val) bfin_write_WDOGA_CNT(val)
#define bfin_write_WDOG_CTL(val) bfin_write_WDOGA_CTL(val)
#define bfin_write_WDOG_STAT(val) bfin_write_WDOGA_STAT(val)
+
+#include "ports.h"
diff --git a/include/asm-blackfin/mach-bf561/ports.h b/include/asm-blackfin/mach-bf561/ports.h
new file mode 100644
index 0000000..194d4a3
--- /dev/null
+++ b/include/asm-blackfin/mach-bf561/ports.h
@@ -0,0 +1,44 @@
+/*
+ * Port Masks
+ */
+
+#ifndef __BFIN_PERIPHERAL_PORT__
+#define __BFIN_PERIPHERAL_PORT__
+
+#include "../mach-common/bits/ports-f.h"
+
+/* The non-standard PF16+ */
+#define PF16 (1 << 0)
+#define PF17 (1 << 1)
+#define PF18 (1 << 2)
+#define PF19 (1 << 3)
+#define PF20 (1 << 4)
+#define PF21 (1 << 5)
+#define PF22 (1 << 6)
+#define PF23 (1 << 7)
+#define PF24 (1 << 8)
+#define PF25 (1 << 9)
+#define PF26 (1 << 10)
+#define PF27 (1 << 11)
+#define PF28 (1 << 12)
+#define PF29 (1 << 13)
+#define PF30 (1 << 14)
+#define PF31 (1 << 15)
+#define PF32 (1 << 0)
+#define PF33 (1 << 1)
+#define PF34 (1 << 2)
+#define PF35 (1 << 3)
+#define PF36 (1 << 4)
+#define PF37 (1 << 5)
+#define PF38 (1 << 6)
+#define PF39 (1 << 7)
+#define PF40 (1 << 8)
+#define PF41 (1 << 9)
+#define PF42 (1 << 10)
+#define PF43 (1 << 11)
+#define PF44 (1 << 12)
+#define PF45 (1 << 13)
+#define PF46 (1 << 14)
+#define PF47 (1 << 15)
+
+#endif