Merge branch 'fixes' into cleanups

Conflicts:

	board/atmel/atngw100/atngw100.c
	board/atmel/atstk1000/atstk1000.c
	cpu/at32ap/at32ap700x/gpio.c
	include/asm-avr32/arch-at32ap700x/clk.h
	include/configs/atngw100.h
	include/configs/atstk1002.h
	include/configs/atstk1003.h
	include/configs/atstk1004.h
	include/configs/atstk1006.h
	include/configs/favr-32-ezkit.h
	include/configs/hammerhead.h
	include/configs/mimc200.h

3 files changed, 13 insertions, 16 deletions

diff --git a/include/asm-blackfin/mach-bf561/BF561_cdef.h b/include/asm-blackfin/mach-bf561/BF561_cdef.h
index 395cd28..d8883f3 100644
--- a/include/asm-blackfin/mach-bf561/BF561_cdef.h
+++ b/include/asm-blackfin/mach-bf561/BF561_cdef.h
@@ -241,9 +241,9 @@
 #define pITEST_DATA1                   ((uint32_t volatile *)ITEST_DATA1)
 #define bfin_read_ITEST_DATA1()        bfin_read32(ITEST_DATA1)
 #define bfin_write_ITEST_DATA1(val)    bfin_write32(ITEST_DATA1, val)
-#define pSICA_SWRST                    ((uint32_t volatile *)SICA_SWRST)
-#define bfin_read_SICA_SWRST()         bfin_read32(SICA_SWRST)
-#define bfin_write_SICA_SWRST(val)     bfin_write32(SICA_SWRST, val)
+#define pSICA_SWRST                    ((uint16_t volatile *)SICA_SWRST)
+#define bfin_read_SICA_SWRST()         bfin_read16(SICA_SWRST)
+#define bfin_write_SICA_SWRST(val)     bfin_write16(SICA_SWRST, val)
 #define pSICA_SYSCR                    ((uint32_t volatile *)SICA_SYSCR)
 #define bfin_read_SICA_SYSCR()         bfin_read32(SICA_SYSCR)
 #define bfin_write_SICA_SYSCR(val)     bfin_write32(SICA_SYSCR, val)
@@ -292,9 +292,9 @@
 #define pSICA_IAR7                     ((uint32_t volatile *)SICA_IAR7)
 #define bfin_read_SICA_IAR7()          bfin_read32(SICA_IAR7)
 #define bfin_write_SICA_IAR7(val)      bfin_write32(SICA_IAR7, val)
-#define pSICB_SWRST                    ((uint32_t volatile *)SICB_SWRST)
-#define bfin_read_SICB_SWRST()         bfin_read32(SICB_SWRST)
-#define bfin_write_SICB_SWRST(val)     bfin_write32(SICB_SWRST, val)
+#define pSICB_SWRST                    ((uint16_t volatile *)SICB_SWRST)
+#define bfin_read_SICB_SWRST()         bfin_read16(SICB_SWRST)
+#define bfin_write_SICB_SWRST(val)     bfin_write16(SICB_SWRST, val)
 #define pSICB_SYSCR                    ((uint32_t volatile *)SICB_SYSCR)
 #define bfin_read_SICB_SYSCR()         bfin_read32(SICB_SYSCR)
 #define bfin_write_SICB_SYSCR(val)     bfin_write32(SICB_SYSCR, val)
@@ -400,12 +400,6 @@
 #define pEVT_OVERRIDE                  ((uint32_t volatile *)EVT_OVERRIDE)
 #define bfin_read_EVT_OVERRIDE()       bfin_read32(EVT_OVERRIDE)
 #define bfin_write_EVT_OVERRIDE(val)   bfin_write32(EVT_OVERRIDE, val)
-#define pDSPID                         ((uint32_t volatile *)DSPID)
-#define bfin_read_DSPID()              bfin_read32(DSPID)
-#define bfin_write_DSPID(val)          bfin_write32(DSPID, val)
-#define pDBGSTAT                       ((uint32_t volatile *)DBGSTAT)
-#define bfin_read_DBGSTAT()            bfin_read32(DBGSTAT)
-#define bfin_write_DBGSTAT(val)        bfin_write32(DBGSTAT, val)
 #define pUART_THR                      ((uint16_t volatile *)UART_THR)
 #define bfin_read_UART_THR()           bfin_read16(UART_THR)
 #define bfin_write_UART_THR(val)       bfin_write16(UART_THR, val)
diff --git a/include/asm-blackfin/mach-bf561/BF561_def.h b/include/asm-blackfin/mach-bf561/BF561_def.h
index 22b5bac..8534962 100644
--- a/include/asm-blackfin/mach-bf561/BF561_def.h
+++ b/include/asm-blackfin/mach-bf561/BF561_def.h
@@ -140,8 +140,6 @@
 #define SRAM_BASE_ADDR_CORE_A          0xFFE00000
 #define SRAM_BASE_ADDR_CORE_B          0xFFE00000
 #define EVT_OVERRIDE                   0xFFE02100
-#define DSPID                          0xFFE05000
-#define DBGSTAT                        0xFFE05008
 #define UART_THR                       0xFFC00400
 #define UART_RBR                       0xFFC00400
 #define UART_DLL                       0xFFC00400
diff --git a/include/asm-blackfin/mach-bf561/anomaly.h b/include/asm-blackfin/mach-bf561/anomaly.h
index 0c1d461..e9c4ca8 100644
--- a/include/asm-blackfin/mach-bf561/anomaly.h
+++ b/include/asm-blackfin/mach-bf561/anomaly.h
@@ -2,12 +2,12 @@
  * File: include/asm-blackfin/mach-bf561/anomaly.h
  * Bugs: Enter bugs at http://blackfin.uclinux.org/
  *
- * Copyright (C) 2004-2007 Analog Devices Inc.
+ * Copyright (C) 2004-2008 Analog Devices Inc.
  * Licensed under the GPL-2 or later.
  */
 
 /* This file shoule be up to date with:
- *  - Revision O, 11/15/2007; ADSP-BF561 Blackfin Processor Anomaly List
+ *  - Revision P, 02/08/2008; ADSP-BF561 Blackfin Processor Anomaly List
  */
 
 #ifndef _MACH_ANOMALY_H_
@@ -256,15 +256,20 @@
 #define ANOMALY_05000357 (1)
 /* Conflicting Column Address Widths Causes SDRAM Errors */
 #define ANOMALY_05000362 (1)
+/* UART Break Signal Issues */
+#define ANOMALY_05000363 (__SILICON_REVISION__ < 5)
 /* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
 #define ANOMALY_05000366 (1)
 /* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
 #define ANOMALY_05000371 (1)
+/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
+#define ANOMALY_05000403 (1)
 
 /* Anomalies that don't exist on this proc */
 #define ANOMALY_05000158 (0)
 #define ANOMALY_05000183 (0)
 #define ANOMALY_05000273 (0)
 #define ANOMALY_05000311 (0)
+#define ANOMALY_05000353 (1)
 
 #endif