punt Blackfin VDSP headers and import sanitized/auto-generated ones

Signed-off-by: Mike Frysinger <vapier@gentoo.org>

4 files changed, 925 insertions, 0 deletions

diff --git a/include/asm-blackfin/mach-bf561/BF561_cdef.h b/include/asm-blackfin/mach-bf561/BF561_cdef.h
new file mode 100644
index 0000000..395cd28
--- /dev/null
+++ b/include/asm-blackfin/mach-bf561/BF561_cdef.h
@@ -0,0 +1,470 @@
+/* DO NOT EDIT THIS FILE
+ * Automatically generated by generate-cdef-headers.xsl
+ * DO NOT EDIT THIS FILE
+ */
+
+#ifndef __BFIN_CDEF_ADSP_BF561_proc__
+#define __BFIN_CDEF_ADSP_BF561_proc__
+
+#include "../mach-common/ADSP-EDN-core_cdef.h"
+
+#include "../mach-common/ADSP-EDN-DUAL-CORE-extended_cdef.h"
+
+#define pSRAM_BASE_ADDR                ((uint32_t volatile *)SRAM_BASE_ADDR)
+#define bfin_read_SRAM_BASE_ADDR()     bfin_read32(SRAM_BASE_ADDR)
+#define bfin_write_SRAM_BASE_ADDR(val) bfin_write32(SRAM_BASE_ADDR, val)
+#define pDMEM_CONTROL                  ((uint32_t volatile *)DMEM_CONTROL)
+#define bfin_read_DMEM_CONTROL()       bfin_read32(DMEM_CONTROL)
+#define bfin_write_DMEM_CONTROL(val)   bfin_write32(DMEM_CONTROL, val)
+#define pDCPLB_STATUS                  ((uint32_t volatile *)DCPLB_STATUS)
+#define bfin_read_DCPLB_STATUS()       bfin_read32(DCPLB_STATUS)
+#define bfin_write_DCPLB_STATUS(val)   bfin_write32(DCPLB_STATUS, val)
+#define pDCPLB_FAULT_ADDR              ((void * volatile *)DCPLB_FAULT_ADDR)
+#define bfin_read_DCPLB_FAULT_ADDR()   bfin_readPTR(DCPLB_FAULT_ADDR)
+#define bfin_write_DCPLB_FAULT_ADDR(val) bfin_writePTR(DCPLB_FAULT_ADDR, val)
+#define pDCPLB_ADDR0                   ((uint32_t volatile *)DCPLB_ADDR0)
+#define bfin_read_DCPLB_ADDR0()        bfin_read32(DCPLB_ADDR0)
+#define bfin_write_DCPLB_ADDR0(val)    bfin_write32(DCPLB_ADDR0, val)
+#define pDCPLB_ADDR1                   ((uint32_t volatile *)DCPLB_ADDR1)
+#define bfin_read_DCPLB_ADDR1()        bfin_read32(DCPLB_ADDR1)
+#define bfin_write_DCPLB_ADDR1(val)    bfin_write32(DCPLB_ADDR1, val)
+#define pDCPLB_ADDR2                   ((uint32_t volatile *)DCPLB_ADDR2)
+#define bfin_read_DCPLB_ADDR2()        bfin_read32(DCPLB_ADDR2)
+#define bfin_write_DCPLB_ADDR2(val)    bfin_write32(DCPLB_ADDR2, val)
+#define pDCPLB_ADDR3                   ((uint32_t volatile *)DCPLB_ADDR3)
+#define bfin_read_DCPLB_ADDR3()        bfin_read32(DCPLB_ADDR3)
+#define bfin_write_DCPLB_ADDR3(val)    bfin_write32(DCPLB_ADDR3, val)
+#define pDCPLB_ADDR4                   ((uint32_t volatile *)DCPLB_ADDR4)
+#define bfin_read_DCPLB_ADDR4()        bfin_read32(DCPLB_ADDR4)
+#define bfin_write_DCPLB_ADDR4(val)    bfin_write32(DCPLB_ADDR4, val)
+#define pDCPLB_ADDR5                   ((uint32_t volatile *)DCPLB_ADDR5)
+#define bfin_read_DCPLB_ADDR5()        bfin_read32(DCPLB_ADDR5)
+#define bfin_write_DCPLB_ADDR5(val)    bfin_write32(DCPLB_ADDR5, val)
+#define pDCPLB_ADDR6                   ((uint32_t volatile *)DCPLB_ADDR6)
+#define bfin_read_DCPLB_ADDR6()        bfin_read32(DCPLB_ADDR6)
+#define bfin_write_DCPLB_ADDR6(val)    bfin_write32(DCPLB_ADDR6, val)
+#define pDCPLB_ADDR7                   ((uint32_t volatile *)DCPLB_ADDR7)
+#define bfin_read_DCPLB_ADDR7()        bfin_read32(DCPLB_ADDR7)
+#define bfin_write_DCPLB_ADDR7(val)    bfin_write32(DCPLB_ADDR7, val)
+#define pDCPLB_ADDR8                   ((uint32_t volatile *)DCPLB_ADDR8)
+#define bfin_read_DCPLB_ADDR8()        bfin_read32(DCPLB_ADDR8)
+#define bfin_write_DCPLB_ADDR8(val)    bfin_write32(DCPLB_ADDR8, val)
+#define pDCPLB_ADDR9                   ((uint32_t volatile *)DCPLB_ADDR9)
+#define bfin_read_DCPLB_ADDR9()        bfin_read32(DCPLB_ADDR9)
+#define bfin_write_DCPLB_ADDR9(val)    bfin_write32(DCPLB_ADDR9, val)
+#define pDCPLB_ADDR10                  ((uint32_t volatile *)DCPLB_ADDR10)
+#define bfin_read_DCPLB_ADDR10()       bfin_read32(DCPLB_ADDR10)
+#define bfin_write_DCPLB_ADDR10(val)   bfin_write32(DCPLB_ADDR10, val)
+#define pDCPLB_ADDR11                  ((uint32_t volatile *)DCPLB_ADDR11)
+#define bfin_read_DCPLB_ADDR11()       bfin_read32(DCPLB_ADDR11)
+#define bfin_write_DCPLB_ADDR11(val)   bfin_write32(DCPLB_ADDR11, val)
+#define pDCPLB_ADDR12                  ((uint32_t volatile *)DCPLB_ADDR12)
+#define bfin_read_DCPLB_ADDR12()       bfin_read32(DCPLB_ADDR12)
+#define bfin_write_DCPLB_ADDR12(val)   bfin_write32(DCPLB_ADDR12, val)
+#define pDCPLB_ADDR13                  ((uint32_t volatile *)DCPLB_ADDR13)
+#define bfin_read_DCPLB_ADDR13()       bfin_read32(DCPLB_ADDR13)
+#define bfin_write_DCPLB_ADDR13(val)   bfin_write32(DCPLB_ADDR13, val)
+#define pDCPLB_ADDR14                  ((uint32_t volatile *)DCPLB_ADDR14)
+#define bfin_read_DCPLB_ADDR14()       bfin_read32(DCPLB_ADDR14)
+#define bfin_write_DCPLB_ADDR14(val)   bfin_write32(DCPLB_ADDR14, val)
+#define pDCPLB_ADDR15                  ((uint32_t volatile *)DCPLB_ADDR15)
+#define bfin_read_DCPLB_ADDR15()       bfin_read32(DCPLB_ADDR15)
+#define bfin_write_DCPLB_ADDR15(val)   bfin_write32(DCPLB_ADDR15, val)
+#define pDCPLB_DATA0                   ((uint32_t volatile *)DCPLB_DATA0)
+#define bfin_read_DCPLB_DATA0()        bfin_read32(DCPLB_DATA0)
+#define bfin_write_DCPLB_DATA0(val)    bfin_write32(DCPLB_DATA0, val)
+#define pDCPLB_DATA1                   ((uint32_t volatile *)DCPLB_DATA1)
+#define bfin_read_DCPLB_DATA1()        bfin_read32(DCPLB_DATA1)
+#define bfin_write_DCPLB_DATA1(val)    bfin_write32(DCPLB_DATA1, val)
+#define pDCPLB_DATA2                   ((uint32_t volatile *)DCPLB_DATA2)
+#define bfin_read_DCPLB_DATA2()        bfin_read32(DCPLB_DATA2)
+#define bfin_write_DCPLB_DATA2(val)    bfin_write32(DCPLB_DATA2, val)
+#define pDCPLB_DATA3                   ((uint32_t volatile *)DCPLB_DATA3)
+#define bfin_read_DCPLB_DATA3()        bfin_read32(DCPLB_DATA3)
+#define bfin_write_DCPLB_DATA3(val)    bfin_write32(DCPLB_DATA3, val)
+#define pDCPLB_DATA4                   ((uint32_t volatile *)DCPLB_DATA4)
+#define bfin_read_DCPLB_DATA4()        bfin_read32(DCPLB_DATA4)
+#define bfin_write_DCPLB_DATA4(val)    bfin_write32(DCPLB_DATA4, val)
+#define pDCPLB_DATA5                   ((uint32_t volatile *)DCPLB_DATA5)
+#define bfin_read_DCPLB_DATA5()        bfin_read32(DCPLB_DATA5)
+#define bfin_write_DCPLB_DATA5(val)    bfin_write32(DCPLB_DATA5, val)
+#define pDCPLB_DATA6                   ((uint32_t volatile *)DCPLB_DATA6)
+#define bfin_read_DCPLB_DATA6()        bfin_read32(DCPLB_DATA6)
+#define bfin_write_DCPLB_DATA6(val)    bfin_write32(DCPLB_DATA6, val)
+#define pDCPLB_DATA7                   ((uint32_t volatile *)DCPLB_DATA7)
+#define bfin_read_DCPLB_DATA7()        bfin_read32(DCPLB_DATA7)
+#define bfin_write_DCPLB_DATA7(val)    bfin_write32(DCPLB_DATA7, val)
+#define pDCPLB_DATA8                   ((uint32_t volatile *)DCPLB_DATA8)
+#define bfin_read_DCPLB_DATA8()        bfin_read32(DCPLB_DATA8)
+#define bfin_write_DCPLB_DATA8(val)    bfin_write32(DCPLB_DATA8, val)
+#define pDCPLB_DATA9                   ((uint32_t volatile *)DCPLB_DATA9)
+#define bfin_read_DCPLB_DATA9()        bfin_read32(DCPLB_DATA9)
+#define bfin_write_DCPLB_DATA9(val)    bfin_write32(DCPLB_DATA9, val)
+#define pDCPLB_DATA10                  ((uint32_t volatile *)DCPLB_DATA10)
+#define bfin_read_DCPLB_DATA10()       bfin_read32(DCPLB_DATA10)
+#define bfin_write_DCPLB_DATA10(val)   bfin_write32(DCPLB_DATA10, val)
+#define pDCPLB_DATA11                  ((uint32_t volatile *)DCPLB_DATA11)
+#define bfin_read_DCPLB_DATA11()       bfin_read32(DCPLB_DATA11)
+#define bfin_write_DCPLB_DATA11(val)   bfin_write32(DCPLB_DATA11, val)
+#define pDCPLB_DATA12                  ((uint32_t volatile *)DCPLB_DATA12)
+#define bfin_read_DCPLB_DATA12()       bfin_read32(DCPLB_DATA12)
+#define bfin_write_DCPLB_DATA12(val)   bfin_write32(DCPLB_DATA12, val)
+#define pDCPLB_DATA13                  ((uint32_t volatile *)DCPLB_DATA13)
+#define bfin_read_DCPLB_DATA13()       bfin_read32(DCPLB_DATA13)
+#define bfin_write_DCPLB_DATA13(val)   bfin_write32(DCPLB_DATA13, val)
+#define pDCPLB_DATA14                  ((uint32_t volatile *)DCPLB_DATA14)
+#define bfin_read_DCPLB_DATA14()       bfin_read32(DCPLB_DATA14)
+#define bfin_write_DCPLB_DATA14(val)   bfin_write32(DCPLB_DATA14, val)
+#define pDCPLB_DATA15                  ((uint32_t volatile *)DCPLB_DATA15)
+#define bfin_read_DCPLB_DATA15()       bfin_read32(DCPLB_DATA15)
+#define bfin_write_DCPLB_DATA15(val)   bfin_write32(DCPLB_DATA15, val)
+#define pDTEST_COMMAND                 ((uint32_t volatile *)DTEST_COMMAND)
+#define bfin_read_DTEST_COMMAND()      bfin_read32(DTEST_COMMAND)
+#define bfin_write_DTEST_COMMAND(val)  bfin_write32(DTEST_COMMAND, val)
+#define pDTEST_DATA0                   ((uint32_t volatile *)DTEST_DATA0)
+#define bfin_read_DTEST_DATA0()        bfin_read32(DTEST_DATA0)
+#define bfin_write_DTEST_DATA0(val)    bfin_write32(DTEST_DATA0, val)
+#define pDTEST_DATA1                   ((uint32_t volatile *)DTEST_DATA1)
+#define bfin_read_DTEST_DATA1()        bfin_read32(DTEST_DATA1)
+#define bfin_write_DTEST_DATA1(val)    bfin_write32(DTEST_DATA1, val)
+#define pIMEM_CONTROL                  ((uint32_t volatile *)IMEM_CONTROL)
+#define bfin_read_IMEM_CONTROL()       bfin_read32(IMEM_CONTROL)
+#define bfin_write_IMEM_CONTROL(val)   bfin_write32(IMEM_CONTROL, val)
+#define pICPLB_STATUS                  ((uint32_t volatile *)ICPLB_STATUS)
+#define bfin_read_ICPLB_STATUS()       bfin_read32(ICPLB_STATUS)
+#define bfin_write_ICPLB_STATUS(val)   bfin_write32(ICPLB_STATUS, val)
+#define pICPLB_FAULT_ADDR              ((uint32_t volatile *)ICPLB_FAULT_ADDR)
+#define bfin_read_ICPLB_FAULT_ADDR()   bfin_read32(ICPLB_FAULT_ADDR)
+#define bfin_write_ICPLB_FAULT_ADDR(val) bfin_write32(ICPLB_FAULT_ADDR, val)
+#define pICPLB_ADDR0                   ((uint32_t volatile *)ICPLB_ADDR0)
+#define bfin_read_ICPLB_ADDR0()        bfin_read32(ICPLB_ADDR0)
+#define bfin_write_ICPLB_ADDR0(val)    bfin_write32(ICPLB_ADDR0, val)
+#define pICPLB_ADDR1                   ((uint32_t volatile *)ICPLB_ADDR1)
+#define bfin_read_ICPLB_ADDR1()        bfin_read32(ICPLB_ADDR1)
+#define bfin_write_ICPLB_ADDR1(val)    bfin_write32(ICPLB_ADDR1, val)
+#define pICPLB_ADDR2                   ((uint32_t volatile *)ICPLB_ADDR2)
+#define bfin_read_ICPLB_ADDR2()        bfin_read32(ICPLB_ADDR2)
+#define bfin_write_ICPLB_ADDR2(val)    bfin_write32(ICPLB_ADDR2, val)
+#define pICPLB_ADDR3                   ((uint32_t volatile *)ICPLB_ADDR3)
+#define bfin_read_ICPLB_ADDR3()        bfin_read32(ICPLB_ADDR3)
+#define bfin_write_ICPLB_ADDR3(val)    bfin_write32(ICPLB_ADDR3, val)
+#define pICPLB_ADDR4                   ((uint32_t volatile *)ICPLB_ADDR4)
+#define bfin_read_ICPLB_ADDR4()        bfin_read32(ICPLB_ADDR4)
+#define bfin_write_ICPLB_ADDR4(val)    bfin_write32(ICPLB_ADDR4, val)
+#define pICPLB_ADDR5                   ((uint32_t volatile *)ICPLB_ADDR5)
+#define bfin_read_ICPLB_ADDR5()        bfin_read32(ICPLB_ADDR5)
+#define bfin_write_ICPLB_ADDR5(val)    bfin_write32(ICPLB_ADDR5, val)
+#define pICPLB_ADDR6                   ((uint32_t volatile *)ICPLB_ADDR6)
+#define bfin_read_ICPLB_ADDR6()        bfin_read32(ICPLB_ADDR6)
+#define bfin_write_ICPLB_ADDR6(val)    bfin_write32(ICPLB_ADDR6, val)
+#define pICPLB_ADDR7                   ((uint32_t volatile *)ICPLB_ADDR7)
+#define bfin_read_ICPLB_ADDR7()        bfin_read32(ICPLB_ADDR7)
+#define bfin_write_ICPLB_ADDR7(val)    bfin_write32(ICPLB_ADDR7, val)
+#define pICPLB_ADDR8                   ((uint32_t volatile *)ICPLB_ADDR8)
+#define bfin_read_ICPLB_ADDR8()        bfin_read32(ICPLB_ADDR8)
+#define bfin_write_ICPLB_ADDR8(val)    bfin_write32(ICPLB_ADDR8, val)
+#define pICPLB_ADDR9                   ((uint32_t volatile *)ICPLB_ADDR9)
+#define bfin_read_ICPLB_ADDR9()        bfin_read32(ICPLB_ADDR9)
+#define bfin_write_ICPLB_ADDR9(val)    bfin_write32(ICPLB_ADDR9, val)
+#define pICPLB_ADDR10                  ((uint32_t volatile *)ICPLB_ADDR10)
+#define bfin_read_ICPLB_ADDR10()       bfin_read32(ICPLB_ADDR10)
+#define bfin_write_ICPLB_ADDR10(val)   bfin_write32(ICPLB_ADDR10, val)
+#define pICPLB_ADDR11                  ((uint32_t volatile *)ICPLB_ADDR11)
+#define bfin_read_ICPLB_ADDR11()       bfin_read32(ICPLB_ADDR11)
+#define bfin_write_ICPLB_ADDR11(val)   bfin_write32(ICPLB_ADDR11, val)
+#define pICPLB_ADDR12                  ((uint32_t volatile *)ICPLB_ADDR12)
+#define bfin_read_ICPLB_ADDR12()       bfin_read32(ICPLB_ADDR12)
+#define bfin_write_ICPLB_ADDR12(val)   bfin_write32(ICPLB_ADDR12, val)
+#define pICPLB_ADDR13                  ((uint32_t volatile *)ICPLB_ADDR13)
+#define bfin_read_ICPLB_ADDR13()       bfin_read32(ICPLB_ADDR13)
+#define bfin_write_ICPLB_ADDR13(val)   bfin_write32(ICPLB_ADDR13, val)
+#define pICPLB_ADDR14                  ((uint32_t volatile *)ICPLB_ADDR14)
+#define bfin_read_ICPLB_ADDR14()       bfin_read32(ICPLB_ADDR14)
+#define bfin_write_ICPLB_ADDR14(val)   bfin_write32(ICPLB_ADDR14, val)
+#define pICPLB_ADDR15                  ((uint32_t volatile *)ICPLB_ADDR15)
+#define bfin_read_ICPLB_ADDR15()       bfin_read32(ICPLB_ADDR15)
+#define bfin_write_ICPLB_ADDR15(val)   bfin_write32(ICPLB_ADDR15, val)
+#define pICPLB_DATA0                   ((uint32_t volatile *)ICPLB_DATA0)
+#define bfin_read_ICPLB_DATA0()        bfin_read32(ICPLB_DATA0)
+#define bfin_write_ICPLB_DATA0(val)    bfin_write32(ICPLB_DATA0, val)
+#define pICPLB_DATA1                   ((uint32_t volatile *)ICPLB_DATA1)
+#define bfin_read_ICPLB_DATA1()        bfin_read32(ICPLB_DATA1)
+#define bfin_write_ICPLB_DATA1(val)    bfin_write32(ICPLB_DATA1, val)
+#define pICPLB_DATA2                   ((uint32_t volatile *)ICPLB_DATA2)
+#define bfin_read_ICPLB_DATA2()        bfin_read32(ICPLB_DATA2)
+#define bfin_write_ICPLB_DATA2(val)    bfin_write32(ICPLB_DATA2, val)
+#define pICPLB_DATA3                   ((uint32_t volatile *)ICPLB_DATA3)
+#define bfin_read_ICPLB_DATA3()        bfin_read32(ICPLB_DATA3)
+#define bfin_write_ICPLB_DATA3(val)    bfin_write32(ICPLB_DATA3, val)
+#define pICPLB_DATA4                   ((uint32_t volatile *)ICPLB_DATA4)
+#define bfin_read_ICPLB_DATA4()        bfin_read32(ICPLB_DATA4)
+#define bfin_write_ICPLB_DATA4(val)    bfin_write32(ICPLB_DATA4, val)
+#define pICPLB_DATA5                   ((uint32_t volatile *)ICPLB_DATA5)
+#define bfin_read_ICPLB_DATA5()        bfin_read32(ICPLB_DATA5)
+#define bfin_write_ICPLB_DATA5(val)    bfin_write32(ICPLB_DATA5, val)
+#define pICPLB_DATA6                   ((uint32_t volatile *)ICPLB_DATA6)
+#define bfin_read_ICPLB_DATA6()        bfin_read32(ICPLB_DATA6)
+#define bfin_write_ICPLB_DATA6(val)    bfin_write32(ICPLB_DATA6, val)
+#define pICPLB_DATA7                   ((uint32_t volatile *)ICPLB_DATA7)
+#define bfin_read_ICPLB_DATA7()        bfin_read32(ICPLB_DATA7)
+#define bfin_write_ICPLB_DATA7(val)    bfin_write32(ICPLB_DATA7, val)
+#define pICPLB_DATA8                   ((uint32_t volatile *)ICPLB_DATA8)
+#define bfin_read_ICPLB_DATA8()        bfin_read32(ICPLB_DATA8)
+#define bfin_write_ICPLB_DATA8(val)    bfin_write32(ICPLB_DATA8, val)
+#define pICPLB_DATA9                   ((uint32_t volatile *)ICPLB_DATA9)
+#define bfin_read_ICPLB_DATA9()        bfin_read32(ICPLB_DATA9)
+#define bfin_write_ICPLB_DATA9(val)    bfin_write32(ICPLB_DATA9, val)
+#define pICPLB_DATA10                  ((uint32_t volatile *)ICPLB_DATA10)
+#define bfin_read_ICPLB_DATA10()       bfin_read32(ICPLB_DATA10)
+#define bfin_write_ICPLB_DATA10(val)   bfin_write32(ICPLB_DATA10, val)
+#define pICPLB_DATA11                  ((uint32_t volatile *)ICPLB_DATA11)
+#define bfin_read_ICPLB_DATA11()       bfin_read32(ICPLB_DATA11)
+#define bfin_write_ICPLB_DATA11(val)   bfin_write32(ICPLB_DATA11, val)
+#define pICPLB_DATA12                  ((uint32_t volatile *)ICPLB_DATA12)
+#define bfin_read_ICPLB_DATA12()       bfin_read32(ICPLB_DATA12)
+#define bfin_write_ICPLB_DATA12(val)   bfin_write32(ICPLB_DATA12, val)
+#define pICPLB_DATA13                  ((uint32_t volatile *)ICPLB_DATA13)
+#define bfin_read_ICPLB_DATA13()       bfin_read32(ICPLB_DATA13)
+#define bfin_write_ICPLB_DATA13(val)   bfin_write32(ICPLB_DATA13, val)
+#define pICPLB_DATA14                  ((uint32_t volatile *)ICPLB_DATA14)
+#define bfin_read_ICPLB_DATA14()       bfin_read32(ICPLB_DATA14)
+#define bfin_write_ICPLB_DATA14(val)   bfin_write32(ICPLB_DATA14, val)
+#define pICPLB_DATA15                  ((uint32_t volatile *)ICPLB_DATA15)
+#define bfin_read_ICPLB_DATA15()       bfin_read32(ICPLB_DATA15)
+#define bfin_write_ICPLB_DATA15(val)   bfin_write32(ICPLB_DATA15, val)
+#define pITEST_COMMAND                 ((uint32_t volatile *)ITEST_COMMAND)
+#define bfin_read_ITEST_COMMAND()      bfin_read32(ITEST_COMMAND)
+#define bfin_write_ITEST_COMMAND(val)  bfin_write32(ITEST_COMMAND, val)
+#define pITEST_DATA0                   ((uint32_t volatile *)ITEST_DATA0)
+#define bfin_read_ITEST_DATA0()        bfin_read32(ITEST_DATA0)
+#define bfin_write_ITEST_DATA0(val)    bfin_write32(ITEST_DATA0, val)
+#define pITEST_DATA1                   ((uint32_t volatile *)ITEST_DATA1)
+#define bfin_read_ITEST_DATA1()        bfin_read32(ITEST_DATA1)
+#define bfin_write_ITEST_DATA1(val)    bfin_write32(ITEST_DATA1, val)
+#define pSICA_SWRST                    ((uint32_t volatile *)SICA_SWRST)
+#define bfin_read_SICA_SWRST()         bfin_read32(SICA_SWRST)
+#define bfin_write_SICA_SWRST(val)     bfin_write32(SICA_SWRST, val)
+#define pSICA_SYSCR                    ((uint32_t volatile *)SICA_SYSCR)
+#define bfin_read_SICA_SYSCR()         bfin_read32(SICA_SYSCR)
+#define bfin_write_SICA_SYSCR(val)     bfin_write32(SICA_SYSCR, val)
+#define pSICA_RVECT                    ((uint16_t volatile *)SICA_RVECT)
+#define bfin_read_SICA_RVECT()         bfin_read16(SICA_RVECT)
+#define bfin_write_SICA_RVECT(val)     bfin_write16(SICA_RVECT, val)
+#define pSICA_IMASK0                   ((uint32_t volatile *)SICA_IMASK0)
+#define bfin_read_SICA_IMASK0()        bfin_read32(SICA_IMASK0)
+#define bfin_write_SICA_IMASK0(val)    bfin_write32(SICA_IMASK0, val)
+#define pSICA_IMASK1                   ((uint32_t volatile *)SICA_IMASK1)
+#define bfin_read_SICA_IMASK1()        bfin_read32(SICA_IMASK1)
+#define bfin_write_SICA_IMASK1(val)    bfin_write32(SICA_IMASK1, val)
+#define pSICA_ISR0                     ((uint32_t volatile *)SICA_ISR0)
+#define bfin_read_SICA_ISR0()          bfin_read32(SICA_ISR0)
+#define bfin_write_SICA_ISR0(val)      bfin_write32(SICA_ISR0, val)
+#define pSICA_ISR1                     ((uint32_t volatile *)SICA_ISR1)
+#define bfin_read_SICA_ISR1()          bfin_read32(SICA_ISR1)
+#define bfin_write_SICA_ISR1(val)      bfin_write32(SICA_ISR1, val)
+#define pSICA_IWR0                     ((uint32_t volatile *)SICA_IWR0)
+#define bfin_read_SICA_IWR0()          bfin_read32(SICA_IWR0)
+#define bfin_write_SICA_IWR0(val)      bfin_write32(SICA_IWR0, val)
+#define pSICA_IWR1                     ((uint32_t volatile *)SICA_IWR1)
+#define bfin_read_SICA_IWR1()          bfin_read32(SICA_IWR1)
+#define bfin_write_SICA_IWR1(val)      bfin_write32(SICA_IWR1, val)
+#define pSICA_IAR0                     ((uint32_t volatile *)SICA_IAR0)
+#define bfin_read_SICA_IAR0()          bfin_read32(SICA_IAR0)
+#define bfin_write_SICA_IAR0(val)      bfin_write32(SICA_IAR0, val)
+#define pSICA_IAR1                     ((uint32_t volatile *)SICA_IAR1)
+#define bfin_read_SICA_IAR1()          bfin_read32(SICA_IAR1)
+#define bfin_write_SICA_IAR1(val)      bfin_write32(SICA_IAR1, val)
+#define pSICA_IAR2                     ((uint32_t volatile *)SICA_IAR2)
+#define bfin_read_SICA_IAR2()          bfin_read32(SICA_IAR2)
+#define bfin_write_SICA_IAR2(val)      bfin_write32(SICA_IAR2, val)
+#define pSICA_IAR3                     ((uint32_t volatile *)SICA_IAR3)
+#define bfin_read_SICA_IAR3()          bfin_read32(SICA_IAR3)
+#define bfin_write_SICA_IAR3(val)      bfin_write32(SICA_IAR3, val)
+#define pSICA_IAR4                     ((uint32_t volatile *)SICA_IAR4)
+#define bfin_read_SICA_IAR4()          bfin_read32(SICA_IAR4)
+#define bfin_write_SICA_IAR4(val)      bfin_write32(SICA_IAR4, val)
+#define pSICA_IAR5                     ((uint32_t volatile *)SICA_IAR5)
+#define bfin_read_SICA_IAR5()          bfin_read32(SICA_IAR5)
+#define bfin_write_SICA_IAR5(val)      bfin_write32(SICA_IAR5, val)
+#define pSICA_IAR6                     ((uint32_t volatile *)SICA_IAR6)
+#define bfin_read_SICA_IAR6()          bfin_read32(SICA_IAR6)
+#define bfin_write_SICA_IAR6(val)      bfin_write32(SICA_IAR6, val)
+#define pSICA_IAR7                     ((uint32_t volatile *)SICA_IAR7)
+#define bfin_read_SICA_IAR7()          bfin_read32(SICA_IAR7)
+#define bfin_write_SICA_IAR7(val)      bfin_write32(SICA_IAR7, val)
+#define pSICB_SWRST                    ((uint32_t volatile *)SICB_SWRST)
+#define bfin_read_SICB_SWRST()         bfin_read32(SICB_SWRST)
+#define bfin_write_SICB_SWRST(val)     bfin_write32(SICB_SWRST, val)
+#define pSICB_SYSCR                    ((uint32_t volatile *)SICB_SYSCR)
+#define bfin_read_SICB_SYSCR()         bfin_read32(SICB_SYSCR)
+#define bfin_write_SICB_SYSCR(val)     bfin_write32(SICB_SYSCR, val)
+#define pSICB_RVECT                    ((uint16_t volatile *)SICB_RVECT)
+#define bfin_read_SICB_RVECT()         bfin_read16(SICB_RVECT)
+#define bfin_write_SICB_RVECT(val)     bfin_write16(SICB_RVECT, val)
+#define pSICB_IMASK0                   ((uint32_t volatile *)SICB_IMASK0)
+#define bfin_read_SICB_IMASK0()        bfin_read32(SICB_IMASK0)
+#define bfin_write_SICB_IMASK0(val)    bfin_write32(SICB_IMASK0, val)
+#define pSICB_IMASK1                   ((uint32_t volatile *)SICB_IMASK1)
+#define bfin_read_SICB_IMASK1()        bfin_read32(SICB_IMASK1)
+#define bfin_write_SICB_IMASK1(val)    bfin_write32(SICB_IMASK1, val)
+#define pSICB_ISR0                     ((uint32_t volatile *)SICB_ISR0)
+#define bfin_read_SICB_ISR0()          bfin_read32(SICB_ISR0)
+#define bfin_write_SICB_ISR0(val)      bfin_write32(SICB_ISR0, val)
+#define pSICB_ISR1                     ((uint32_t volatile *)SICB_ISR1)
+#define bfin_read_SICB_ISR1()          bfin_read32(SICB_ISR1)
+#define bfin_write_SICB_ISR1(val)      bfin_write32(SICB_ISR1, val)
+#define pSICB_IWR0                     ((uint32_t volatile *)SICB_IWR0)
+#define bfin_read_SICB_IWR0()          bfin_read32(SICB_IWR0)
+#define bfin_write_SICB_IWR0(val)      bfin_write32(SICB_IWR0, val)
+#define pSICB_IWR1                     ((uint32_t volatile *)SICB_IWR1)
+#define bfin_read_SICB_IWR1()          bfin_read32(SICB_IWR1)
+#define bfin_write_SICB_IWR1(val)      bfin_write32(SICB_IWR1, val)
+#define pSICB_IAR0                     ((uint32_t volatile *)SICB_IAR0)
+#define bfin_read_SICB_IAR0()          bfin_read32(SICB_IAR0)
+#define bfin_write_SICB_IAR0(val)      bfin_write32(SICB_IAR0, val)
+#define pSICB_IAR1                     ((uint32_t volatile *)SICB_IAR1)
+#define bfin_read_SICB_IAR1()          bfin_read32(SICB_IAR1)
+#define bfin_write_SICB_IAR1(val)      bfin_write32(SICB_IAR1, val)
+#define pSICB_IAR2                     ((uint32_t volatile *)SICB_IAR2)
+#define bfin_read_SICB_IAR2()          bfin_read32(SICB_IAR2)
+#define bfin_write_SICB_IAR2(val)      bfin_write32(SICB_IAR2, val)
+#define pSICB_IAR3                     ((uint32_t volatile *)SICB_IAR3)
+#define bfin_read_SICB_IAR3()          bfin_read32(SICB_IAR3)
+#define bfin_write_SICB_IAR3(val)      bfin_write32(SICB_IAR3, val)
+#define pSICB_IAR4                     ((uint32_t volatile *)SICB_IAR4)
+#define bfin_read_SICB_IAR4()          bfin_read32(SICB_IAR4)
+#define bfin_write_SICB_IAR4(val)      bfin_write32(SICB_IAR4, val)
+#define pSICB_IAR5                     ((uint32_t volatile *)SICB_IAR5)
+#define bfin_read_SICB_IAR5()          bfin_read32(SICB_IAR5)
+#define bfin_write_SICB_IAR5(val)      bfin_write32(SICB_IAR5, val)
+#define pSICB_IAR6                     ((uint32_t volatile *)SICB_IAR6)
+#define bfin_read_SICB_IAR6()          bfin_read32(SICB_IAR6)
+#define bfin_write_SICB_IAR6(val)      bfin_write32(SICB_IAR6, val)
+#define pSICB_IAR7                     ((uint32_t volatile *)SICB_IAR7)
+#define bfin_read_SICB_IAR7()          bfin_read32(SICB_IAR7)
+#define bfin_write_SICB_IAR7(val)      bfin_write32(SICB_IAR7, val)
+#define pPPI0_CONTROL                  ((uint16_t volatile *)PPI0_CONTROL)
+#define bfin_read_PPI0_CONTROL()       bfin_read16(PPI0_CONTROL)
+#define bfin_write_PPI0_CONTROL(val)   bfin_write16(PPI0_CONTROL, val)
+#define pPPI0_STATUS                   ((uint16_t volatile *)PPI0_STATUS)
+#define bfin_read_PPI0_STATUS()        bfin_read16(PPI0_STATUS)
+#define bfin_write_PPI0_STATUS(val)    bfin_write16(PPI0_STATUS, val)
+#define pPPI0_DELAY                    ((uint16_t volatile *)PPI0_DELAY)
+#define bfin_read_PPI0_DELAY()         bfin_read16(PPI0_DELAY)
+#define bfin_write_PPI0_DELAY(val)     bfin_write16(PPI0_DELAY, val)
+#define pPPI0_COUNT                    ((uint16_t volatile *)PPI0_COUNT)
+#define bfin_read_PPI0_COUNT()         bfin_read16(PPI0_COUNT)
+#define bfin_write_PPI0_COUNT(val)     bfin_write16(PPI0_COUNT, val)
+#define pPPI0_FRAME                    ((uint16_t volatile *)PPI0_FRAME)
+#define bfin_read_PPI0_FRAME()         bfin_read16(PPI0_FRAME)
+#define bfin_write_PPI0_FRAME(val)     bfin_write16(PPI0_FRAME, val)
+#define pPPI1_CONTROL                  ((uint16_t volatile *)PPI1_CONTROL)
+#define bfin_read_PPI1_CONTROL()       bfin_read16(PPI1_CONTROL)
+#define bfin_write_PPI1_CONTROL(val)   bfin_write16(PPI1_CONTROL, val)
+#define pPPI1_STATUS                   ((uint16_t volatile *)PPI1_STATUS)
+#define bfin_read_PPI1_STATUS()        bfin_read16(PPI1_STATUS)
+#define bfin_write_PPI1_STATUS(val)    bfin_write16(PPI1_STATUS, val)
+#define pPPI1_DELAY                    ((uint16_t volatile *)PPI1_DELAY)
+#define bfin_read_PPI1_DELAY()         bfin_read16(PPI1_DELAY)
+#define bfin_write_PPI1_DELAY(val)     bfin_write16(PPI1_DELAY, val)
+#define pPPI1_COUNT                    ((uint16_t volatile *)PPI1_COUNT)
+#define bfin_read_PPI1_COUNT()         bfin_read16(PPI1_COUNT)
+#define bfin_write_PPI1_COUNT(val)     bfin_write16(PPI1_COUNT, val)
+#define pPPI1_FRAME                    ((uint16_t volatile *)PPI1_FRAME)
+#define bfin_read_PPI1_FRAME()         bfin_read16(PPI1_FRAME)
+#define bfin_write_PPI1_FRAME(val)     bfin_write16(PPI1_FRAME, val)
+#define pTBUFCTL                       ((uint32_t volatile *)TBUFCTL)
+#define bfin_read_TBUFCTL()            bfin_read32(TBUFCTL)
+#define bfin_write_TBUFCTL(val)        bfin_write32(TBUFCTL, val)
+#define pTBUFSTAT                      ((uint32_t volatile *)TBUFSTAT)
+#define bfin_read_TBUFSTAT()           bfin_read32(TBUFSTAT)
+#define bfin_write_TBUFSTAT(val)       bfin_write32(TBUFSTAT, val)
+#define pTBUF                          ((uint32_t volatile *)TBUF)
+#define bfin_read_TBUF()               bfin_read32(TBUF)
+#define bfin_write_TBUF(val)           bfin_write32(TBUF, val)
+#define pPFCTL                         ((uint32_t volatile *)PFCTL)
+#define bfin_read_PFCTL()              bfin_read32(PFCTL)
+#define bfin_write_PFCTL(val)          bfin_write32(PFCTL, val)
+#define pPFCNTR0                       ((uint32_t volatile *)PFCNTR0)
+#define bfin_read_PFCNTR0()            bfin_read32(PFCNTR0)
+#define bfin_write_PFCNTR0(val)        bfin_write32(PFCNTR0, val)
+#define pPFCNTR1                       ((uint32_t volatile *)PFCNTR1)
+#define bfin_read_PFCNTR1()            bfin_read32(PFCNTR1)
+#define bfin_write_PFCNTR1(val)        bfin_write32(PFCNTR1, val)
+#define pSRAM_BASE_ADDR_CORE_A         ((uint32_t volatile *)SRAM_BASE_ADDR_CORE_A)
+#define bfin_read_SRAM_BASE_ADDR_CORE_A() bfin_read32(SRAM_BASE_ADDR_CORE_A)
+#define bfin_write_SRAM_BASE_ADDR_CORE_A(val) bfin_write32(SRAM_BASE_ADDR_CORE_A, val)
+#define pSRAM_BASE_ADDR_CORE_B         ((uint32_t volatile *)SRAM_BASE_ADDR_CORE_B)
+#define bfin_read_SRAM_BASE_ADDR_CORE_B() bfin_read32(SRAM_BASE_ADDR_CORE_B)
+#define bfin_write_SRAM_BASE_ADDR_CORE_B(val) bfin_write32(SRAM_BASE_ADDR_CORE_B, val)
+#define pEVT_OVERRIDE                  ((uint32_t volatile *)EVT_OVERRIDE)
+#define bfin_read_EVT_OVERRIDE()       bfin_read32(EVT_OVERRIDE)
+#define bfin_write_EVT_OVERRIDE(val)   bfin_write32(EVT_OVERRIDE, val)
+#define pDSPID                         ((uint32_t volatile *)DSPID)
+#define bfin_read_DSPID()              bfin_read32(DSPID)
+#define bfin_write_DSPID(val)          bfin_write32(DSPID, val)
+#define pDBGSTAT                       ((uint32_t volatile *)DBGSTAT)
+#define bfin_read_DBGSTAT()            bfin_read32(DBGSTAT)
+#define bfin_write_DBGSTAT(val)        bfin_write32(DBGSTAT, val)
+#define pUART_THR                      ((uint16_t volatile *)UART_THR)
+#define bfin_read_UART_THR()           bfin_read16(UART_THR)
+#define bfin_write_UART_THR(val)       bfin_write16(UART_THR, val)
+#define pUART_RBR                      ((uint16_t volatile *)UART_RBR)
+#define bfin_read_UART_RBR()           bfin_read16(UART_RBR)
+#define bfin_write_UART_RBR(val)       bfin_write16(UART_RBR, val)
+#define pUART_DLL                      ((uint16_t volatile *)UART_DLL)
+#define bfin_read_UART_DLL()           bfin_read16(UART_DLL)
+#define bfin_write_UART_DLL(val)       bfin_write16(UART_DLL, val)
+#define pUART_DLH                      ((uint16_t volatile *)UART_DLH)
+#define bfin_read_UART_DLH()           bfin_read16(UART_DLH)
+#define bfin_write_UART_DLH(val)       bfin_write16(UART_DLH, val)
+#define pUART_IER                      ((uint16_t volatile *)UART_IER)
+#define bfin_read_UART_IER()           bfin_read16(UART_IER)
+#define bfin_write_UART_IER(val)       bfin_write16(UART_IER, val)
+#define pUART_IIR                      ((uint16_t volatile *)UART_IIR)
+#define bfin_read_UART_IIR()           bfin_read16(UART_IIR)
+#define bfin_write_UART_IIR(val)       bfin_write16(UART_IIR, val)
+#define pUART_LCR                      ((uint16_t volatile *)UART_LCR)
+#define bfin_read_UART_LCR()           bfin_read16(UART_LCR)
+#define bfin_write_UART_LCR(val)       bfin_write16(UART_LCR, val)
+#define pUART_MCR                      ((uint16_t volatile *)UART_MCR)
+#define bfin_read_UART_MCR()           bfin_read16(UART_MCR)
+#define bfin_write_UART_MCR(val)       bfin_write16(UART_MCR, val)
+#define pUART_LSR                      ((uint16_t volatile *)UART_LSR)
+#define bfin_read_UART_LSR()           bfin_read16(UART_LSR)
+#define bfin_write_UART_LSR(val)       bfin_write16(UART_LSR, val)
+#define pUART_MSR                      ((uint16_t volatile *)UART_MSR)
+#define bfin_read_UART_MSR()           bfin_read16(UART_MSR)
+#define bfin_write_UART_MSR(val)       bfin_write16(UART_MSR, val)
+#define pUART_SCR                      ((uint16_t volatile *)UART_SCR)
+#define bfin_read_UART_SCR()           bfin_read16(UART_SCR)
+#define bfin_write_UART_SCR(val)       bfin_write16(UART_SCR, val)
+#define pUART_GCTL                     ((uint16_t volatile *)UART_GCTL)
+#define bfin_read_UART_GCTL()          bfin_read16(UART_GCTL)
+#define bfin_write_UART_GCTL(val)      bfin_write16(UART_GCTL, val)
+#define pUART_GBL                      ((uint16_t volatile *)UART_GBL)
+#define bfin_read_UART_GBL()           bfin_read16(UART_GBL)
+#define bfin_write_UART_GBL(val)       bfin_write16(UART_GBL, val)
+#define pEBIU_AMGCTL                   ((uint16_t volatile *)EBIU_AMGCTL)
+#define bfin_read_EBIU_AMGCTL()        bfin_read16(EBIU_AMGCTL)
+#define bfin_write_EBIU_AMGCTL(val)    bfin_write16(EBIU_AMGCTL, val)
+#define pEBIU_AMBCTL0                  ((uint32_t volatile *)EBIU_AMBCTL0)
+#define bfin_read_EBIU_AMBCTL0()       bfin_read32(EBIU_AMBCTL0)
+#define bfin_write_EBIU_AMBCTL0(val)   bfin_write32(EBIU_AMBCTL0, val)
+#define pEBIU_AMBCTL1                  ((uint32_t volatile *)EBIU_AMBCTL1)
+#define bfin_read_EBIU_AMBCTL1()       bfin_read32(EBIU_AMBCTL1)
+#define bfin_write_EBIU_AMBCTL1(val)   bfin_write32(EBIU_AMBCTL1, val)
+#define pEBIU_SDGCTL                   ((uint32_t volatile *)EBIU_SDGCTL)
+#define bfin_read_EBIU_SDGCTL()        bfin_read32(EBIU_SDGCTL)
+#define bfin_write_EBIU_SDGCTL(val)    bfin_write32(EBIU_SDGCTL, val)
+#define pEBIU_SDBCTL                   ((uint32_t volatile *)EBIU_SDBCTL)
+#define bfin_read_EBIU_SDBCTL()        bfin_read32(EBIU_SDBCTL)
+#define bfin_write_EBIU_SDBCTL(val)    bfin_write32(EBIU_SDBCTL, val)
+#define pEBIU_SDRRC                    ((uint16_t volatile *)EBIU_SDRRC)
+#define bfin_read_EBIU_SDRRC()         bfin_read16(EBIU_SDRRC)
+#define bfin_write_EBIU_SDRRC(val)     bfin_write16(EBIU_SDRRC, val)
+#define pEBIU_SDSTAT                   ((uint16_t volatile *)EBIU_SDSTAT)
+#define bfin_read_EBIU_SDSTAT()        bfin_read16(EBIU_SDSTAT)
+#define bfin_write_EBIU_SDSTAT(val)    bfin_write16(EBIU_SDSTAT, val)
+
+#endif /* __BFIN_CDEF_ADSP_BF561_proc__ */
diff --git a/include/asm-blackfin/mach-bf561/BF561_def.h b/include/asm-blackfin/mach-bf561/BF561_def.h
new file mode 100644
index 0000000..22b5bac
--- /dev/null
+++ b/include/asm-blackfin/mach-bf561/BF561_def.h
@@ -0,0 +1,175 @@
+/* DO NOT EDIT THIS FILE
+ * Automatically generated by generate-def-headers.xsl
+ * DO NOT EDIT THIS FILE
+ */
+
+#ifndef __BFIN_DEF_ADSP_BF561_proc__
+#define __BFIN_DEF_ADSP_BF561_proc__
+
+#include "../mach-common/ADSP-EDN-core_def.h"
+
+#include "../mach-common/ADSP-EDN-DUAL-CORE-extended_def.h"
+
+#define SRAM_BASE_ADDR                 0xFFE00000
+#define DMEM_CONTROL                   0xFFE00004
+#define DCPLB_STATUS                   0xFFE00008
+#define DCPLB_FAULT_ADDR               0xFFE0000C
+#define DCPLB_ADDR0                    0xFFE00100
+#define DCPLB_ADDR1                    0xFFE00104
+#define DCPLB_ADDR2                    0xFFE00108
+#define DCPLB_ADDR3                    0xFFE0010C
+#define DCPLB_ADDR4                    0xFFE00110
+#define DCPLB_ADDR5                    0xFFE00114
+#define DCPLB_ADDR6                    0xFFE00118
+#define DCPLB_ADDR7                    0xFFE0011C
+#define DCPLB_ADDR8                    0xFFE00120
+#define DCPLB_ADDR9                    0xFFE00124
+#define DCPLB_ADDR10                   0xFFE00128
+#define DCPLB_ADDR11                   0xFFE0012C
+#define DCPLB_ADDR12                   0xFFE00130
+#define DCPLB_ADDR13                   0xFFE00134
+#define DCPLB_ADDR14                   0xFFE00138
+#define DCPLB_ADDR15                   0xFFE0013C
+#define DCPLB_DATA0                    0xFFE00200
+#define DCPLB_DATA1                    0xFFE00204
+#define DCPLB_DATA2                    0xFFE00208
+#define DCPLB_DATA3                    0xFFE0020C
+#define DCPLB_DATA4                    0xFFE00210
+#define DCPLB_DATA5                    0xFFE00214
+#define DCPLB_DATA6                    0xFFE00218
+#define DCPLB_DATA7                    0xFFE0021C
+#define DCPLB_DATA8                    0xFFE00220
+#define DCPLB_DATA9                    0xFFE00224
+#define DCPLB_DATA10                   0xFFE00228
+#define DCPLB_DATA11                   0xFFE0022C
+#define DCPLB_DATA12                   0xFFE00230
+#define DCPLB_DATA13                   0xFFE00234
+#define DCPLB_DATA14                   0xFFE00238
+#define DCPLB_DATA15                   0xFFE0023C
+#define DTEST_COMMAND                  0xFFE00300
+#define DTEST_DATA0                    0xFFE00400
+#define DTEST_DATA1                    0xFFE00404
+#define IMEM_CONTROL                   0xFFE01004
+#define ICPLB_STATUS                   0xFFE01008
+#define ICPLB_FAULT_ADDR               0xFFE0100C
+#define ICPLB_ADDR0                    0xFFE01100
+#define ICPLB_ADDR1                    0xFFE01104
+#define ICPLB_ADDR2                    0xFFE01108
+#define ICPLB_ADDR3                    0xFFE0110C
+#define ICPLB_ADDR4                    0xFFE01110
+#define ICPLB_ADDR5                    0xFFE01114
+#define ICPLB_ADDR6                    0xFFE01118
+#define ICPLB_ADDR7                    0xFFE0111C
+#define ICPLB_ADDR8                    0xFFE01120
+#define ICPLB_ADDR9                    0xFFE01124
+#define ICPLB_ADDR10                   0xFFE01128
+#define ICPLB_ADDR11                   0xFFE0112C
+#define ICPLB_ADDR12                   0xFFE01130
+#define ICPLB_ADDR13                   0xFFE01134
+#define ICPLB_ADDR14                   0xFFE01138
+#define ICPLB_ADDR15                   0xFFE0113C
+#define ICPLB_DATA0                    0xFFE01200
+#define ICPLB_DATA1                    0xFFE01204
+#define ICPLB_DATA2                    0xFFE01208
+#define ICPLB_DATA3                    0xFFE0120C
+#define ICPLB_DATA4                    0xFFE01210
+#define ICPLB_DATA5                    0xFFE01214
+#define ICPLB_DATA6                    0xFFE01218
+#define ICPLB_DATA7                    0xFFE0121C
+#define ICPLB_DATA8                    0xFFE01220
+#define ICPLB_DATA9                    0xFFE01224
+#define ICPLB_DATA10                   0xFFE01228
+#define ICPLB_DATA11                   0xFFE0122C
+#define ICPLB_DATA12                   0xFFE01230
+#define ICPLB_DATA13                   0xFFE01234
+#define ICPLB_DATA14                   0xFFE01238
+#define ICPLB_DATA15                   0xFFE0123C
+#define ITEST_COMMAND                  0xFFE01300
+#define ITEST_DATA0                    0xFFE01400
+#define ITEST_DATA1                    0xFFE01404
+#define SICA_SWRST                     0xFFC00100
+#define SICA_SYSCR                     0xFFC00104
+#define SICA_RVECT                     0xFFC00108
+#define SICA_IMASK0                    0xFFC0010C
+#define SICA_IMASK1                    0xFFC00110
+#define SICA_ISR0                      0xFFC00114
+#define SICA_ISR1                      0xFFC00118
+#define SICA_IWR0                      0xFFC0011C
+#define SICA_IWR1                      0xFFC00120
+#define SICA_IAR0                      0xFFC00124
+#define SICA_IAR1                      0xFFC00128
+#define SICA_IAR2                      0xFFC0012C
+#define SICA_IAR3                      0xFFC00130
+#define SICA_IAR4                      0xFFC00134
+#define SICA_IAR5                      0xFFC00138
+#define SICA_IAR6                      0xFFC0013C
+#define SICA_IAR7                      0xFFC00140
+#define SICB_SWRST                     0xFFC01100
+#define SICB_SYSCR                     0xFFC01104
+#define SICB_RVECT                     0xFFC01108
+#define SICB_IMASK0                    0xFFC0110C
+#define SICB_IMASK1                    0xFFC01110
+#define SICB_ISR0                      0xFFC01114
+#define SICB_ISR1                      0xFFC01118
+#define SICB_IWR0                      0xFFC0111C
+#define SICB_IWR1                      0xFFC01120
+#define SICB_IAR0                      0xFFC01124
+#define SICB_IAR1                      0xFFC01128
+#define SICB_IAR2                      0xFFC0112C
+#define SICB_IAR3                      0xFFC01130
+#define SICB_IAR4                      0xFFC01134
+#define SICB_IAR5                      0xFFC01138
+#define SICB_IAR6                      0xFFC0113C
+#define SICB_IAR7                      0xFFC01140
+#define PPI0_CONTROL                   0xFFC01000
+#define PPI0_STATUS                    0xFFC01004
+#define PPI0_DELAY                     0xFFC0100C
+#define PPI0_COUNT                     0xFFC01008
+#define PPI0_FRAME                     0xFFC01010
+#define PPI1_CONTROL                   0xFFC01300
+#define PPI1_STATUS                    0xFFC01304
+#define PPI1_DELAY                     0xFFC0130C
+#define PPI1_COUNT                     0xFFC01308
+#define PPI1_FRAME                     0xFFC01310
+#define TBUFCTL                        0xFFE06000
+#define TBUFSTAT                       0xFFE06004
+#define TBUF                           0xFFE06100
+#define PFCTL                          0xFFE08000
+#define PFCNTR0                        0xFFE08100
+#define PFCNTR1                        0xFFE08104
+#define SRAM_BASE_ADDR_CORE_A          0xFFE00000
+#define SRAM_BASE_ADDR_CORE_B          0xFFE00000
+#define EVT_OVERRIDE                   0xFFE02100
+#define DSPID                          0xFFE05000
+#define DBGSTAT                        0xFFE05008
+#define UART_THR                       0xFFC00400
+#define UART_RBR                       0xFFC00400
+#define UART_DLL                       0xFFC00400
+#define UART_DLH                       0xFFC00404
+#define UART_IER                       0xFFC00404
+#define UART_IIR                       0xFFC00408
+#define UART_LCR                       0xFFC0040C
+#define UART_MCR                       0xFFC00410
+#define UART_LSR                       0xFFC00414
+#define UART_MSR                       0xFFC00418
+#define UART_SCR                       0xFFC0041C
+#define UART_GCTL                      0xFFC00424
+#define UART_GBL                       0xFFC00424
+#define EBIU_AMGCTL                    0xFFC00A00
+#define EBIU_AMBCTL0                   0xFFC00A04
+#define EBIU_AMBCTL1                   0xFFC00A08
+#define EBIU_SDGCTL                    0xFFC00A10
+#define EBIU_SDBCTL                    0xFFC00A14
+#define EBIU_SDRRC                     0xFFC00A18
+#define EBIU_SDSTAT                    0xFFC00A1C
+#define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000 -> 0xFFA03FFF Instruction Bank A SRAM */
+#define L1_INST_SRAM_SIZE (0xFFA03FFF - 0xFFA00000 + 1)
+#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE)
+#define L1_SRAM_SCRATCH 0xFFB00000 /* 0xFFB00000 -> 0xFFB00FFF Scratchpad SRAM */
+#define L1_SRAM_SCRATCH_SIZE (0xFFB00FFF - 0xFFB00000 + 1)
+#define L1_SRAM_SCRATCH_END (L1_SRAM_SCRATCH + L1_SRAM_SCRATCH_SIZE)
+#define SYSMMR_BASE 0xFFC00000 /* 0xFFC00000 -> 0xFFFFFFFF MMR registers */
+#define SYSMMR_BASE_SIZE (0xFFFFFFFF - 0xFFC00000 + 1)
+#define SYSMMR_BASE_END (SYSMMR_BASE + SYSMMR_BASE_SIZE)
+
+#endif /* __BFIN_DEF_ADSP_BF561_proc__ */
diff --git a/include/asm-blackfin/mach-bf561/anomaly.h b/include/asm-blackfin/mach-bf561/anomaly.h
new file mode 100644
index 0000000..0c1d461
--- /dev/null
+++ b/include/asm-blackfin/mach-bf561/anomaly.h
@@ -0,0 +1,270 @@
+/*
+ * File: include/asm-blackfin/mach-bf561/anomaly.h
+ * Bugs: Enter bugs at http://blackfin.uclinux.org/
+ *
+ * Copyright (C) 2004-2007 Analog Devices Inc.
+ * Licensed under the GPL-2 or later.
+ */
+
+/* This file shoule be up to date with:
+ *  - Revision O, 11/15/2007; ADSP-BF561 Blackfin Processor Anomaly List
+ */
+
+#ifndef _MACH_ANOMALY_H_
+#define _MACH_ANOMALY_H_
+
+/* We do not support 0.1, 0.2, or 0.4 silicon - sorry */
+#if __SILICON_REVISION__ < 3 || __SILICON_REVISION__ == 4
+# error will not work on BF561 silicon version 0.0, 0.1, 0.2, or 0.4
+#endif
+
+/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot 2 Not Supported */
+#define ANOMALY_05000074 (1)
+/* UART Line Status Register (UART_LSR) Bits Are Not Updated at the Same Time */
+#define ANOMALY_05000099 (__SILICON_REVISION__ < 5)
+/* Trace Buffers may contain errors in emulation mode and/or exception, NMI, reset handlers */
+#define ANOMALY_05000116 (__SILICON_REVISION__ < 3)
+/* Testset instructions restricted to 32-bit aligned memory locations */
+#define ANOMALY_05000120 (1)
+/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
+#define ANOMALY_05000122 (1)
+/* Erroneous exception when enabling cache */
+#define ANOMALY_05000125 (__SILICON_REVISION__ < 3)
+/* Signbits instruction not functional under certain conditions */
+#define ANOMALY_05000127 (1)
+/* Two bits in the Watchpoint Status Register (WPSTAT) are swapped */
+#define ANOMALY_05000134 (__SILICON_REVISION__ < 3)
+/* Enable wires from the Data Watchpoint Address Control Register (WPDACTL) are swapped */
+#define ANOMALY_05000135 (__SILICON_REVISION__ < 3)
+/* Stall in multi-unit DMA operations */
+#define ANOMALY_05000136 (__SILICON_REVISION__ < 3)
+/* Allowing the SPORT RX FIFO to fill will cause an overflow */
+#define ANOMALY_05000140 (__SILICON_REVISION__ < 3)
+/* Infinite Stall may occur with a particular sequence of consecutive dual dag events */
+#define ANOMALY_05000141 (__SILICON_REVISION__ < 3)
+/* Interrupts may be lost when a programmable input flag is configured to be edge sensitive */
+#define ANOMALY_05000142 (__SILICON_REVISION__ < 3)
+/* DMA and TESTSET conflict when both are accessing external memory */
+#define ANOMALY_05000144 (__SILICON_REVISION__ < 3)
+/* In PWM_OUT mode, you must enable the PPI block to generate a waveform from PPI_CLK */
+#define ANOMALY_05000145 (__SILICON_REVISION__ < 3)
+/* MDMA may lose the first few words of a descriptor chain */
+#define ANOMALY_05000146 (__SILICON_REVISION__ < 3)
+/* Source MDMA descriptor may stop with a DMA Error near beginning of descriptor fetch */
+#define ANOMALY_05000147 (__SILICON_REVISION__ < 3)
+/* IMDMA S1/D1 channel may stall */
+#define ANOMALY_05000149 (1)
+/* DMA engine may lose data due to incorrect handshaking */
+#define ANOMALY_05000150 (__SILICON_REVISION__ < 3)
+/* DMA stalls when all three controllers read data from the same source */
+#define ANOMALY_05000151 (__SILICON_REVISION__ < 3)
+/* Execution stall when executing in L2 and doing external accesses */
+#define ANOMALY_05000152 (__SILICON_REVISION__ < 3)
+/* Frame Delay in SPORT Multichannel Mode */
+#define ANOMALY_05000153 (__SILICON_REVISION__ < 3)
+/* SPORT TFS signal stays active in multichannel mode outside of valid channels */
+#define ANOMALY_05000154 (__SILICON_REVISION__ < 3)
+/* Timers in PWM-Out Mode with PPI GP Receive (Input) Mode with 0 Frame Syncs */
+#define ANOMALY_05000156 (__SILICON_REVISION__ < 4)
+/* Killed 32-bit MMR write leads to next system MMR access thinking it should be 32-bit */
+#define ANOMALY_05000157 (__SILICON_REVISION__ < 3)
+/* DMA Lock-up at CCLK to SCLK ratios of 4:1, 2:1, or 1:1 */
+#define ANOMALY_05000159 (__SILICON_REVISION__ < 3)
+/* A read from external memory may return a wrong value with data cache enabled */
+#define ANOMALY_05000160 (__SILICON_REVISION__ < 3)
+/* Data Cache Fill data can be corrupted after/during Instruction DMA if certain core stalls exist */
+#define ANOMALY_05000161 (__SILICON_REVISION__ < 3)
+/* DMEM_CONTROL<12> is not set on Reset */
+#define ANOMALY_05000162 (__SILICON_REVISION__ < 3)
+/* SPORT transmit data is not gated by external frame sync in certain conditions */
+#define ANOMALY_05000163 (__SILICON_REVISION__ < 3)
+/* PPI Data Lengths Between 8 and 16 Do Not Zero Out Upper Bits */
+#define ANOMALY_05000166 (1)
+/* Turning Serial Ports on with External Frame Syncs */
+#define ANOMALY_05000167 (1)
+/* SDRAM auto-refresh and subsequent Power Ups */
+#define ANOMALY_05000168 (__SILICON_REVISION__ < 5)
+/* DATA CPLB page miss can result in lost write-through cache data writes */
+#define ANOMALY_05000169 (__SILICON_REVISION__ < 5)
+/* Boot-ROM code modifies SICA_IWRx wakeup registers */
+#define ANOMALY_05000171 (__SILICON_REVISION__ < 5)
+/* DSPID register values incorrect */
+#define ANOMALY_05000172 (__SILICON_REVISION__ < 3)
+/* DMA vs Core accesses to external memory */
+#define ANOMALY_05000173 (__SILICON_REVISION__ < 3)
+/* Cache Fill Buffer Data lost */
+#define ANOMALY_05000174 (__SILICON_REVISION__ < 5)
+/* Overlapping Sequencer and Memory Stalls */
+#define ANOMALY_05000175 (__SILICON_REVISION__ < 5)
+/* Multiplication of (-1) by (-1) followed by an accumulator saturation */
+#define ANOMALY_05000176 (__SILICON_REVISION__ < 5)
+/* PPI_COUNT Cannot Be Programmed to 0 in General Purpose TX or RX Modes */
+#define ANOMALY_05000179 (__SILICON_REVISION__ < 5)
+/* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */
+#define ANOMALY_05000180 (1)
+/* Disabling the PPI resets the PPI configuration registers */
+#define ANOMALY_05000181 (__SILICON_REVISION__ < 5)
+/* IMDMA does not operate to full speed for 600MHz and higher devices */
+#define ANOMALY_05000182 (1)
+/* Timer Pin limitations for PPI TX Modes with External Frame Syncs */
+#define ANOMALY_05000184 (__SILICON_REVISION__ < 5)
+/* PPI TX Mode with 2 External Frame Syncs */
+#define ANOMALY_05000185 (__SILICON_REVISION__ < 5)
+/* PPI packing with Data Length greater than 8 bits (not a meaningful mode) */
+#define ANOMALY_05000186 (__SILICON_REVISION__ < 5)
+/* IMDMA Corrupted Data after a Halt */
+#define ANOMALY_05000187 (1)
+/* IMDMA Restrictions on Descriptor and Buffer Placement in Memory */
+#define ANOMALY_05000188 (__SILICON_REVISION__ < 5)
+/* False Protection Exceptions */
+#define ANOMALY_05000189 (__SILICON_REVISION__ < 5)
+/* PPI not functional at core voltage < 1Volt */
+#define ANOMALY_05000190 (1)
+/* PPI does not invert the Driving PPICLK edge in Transmit Modes */
+#define ANOMALY_05000191 (__SILICON_REVISION__ < 3)
+/* False I/O Pin Interrupts on Edge-Sensitive Inputs When Polarity Setting Is Changed */
+#define ANOMALY_05000193 (__SILICON_REVISION__ < 5)
+/* Restarting SPORT in Specific Modes May Cause Data Corruption */
+#define ANOMALY_05000194 (__SILICON_REVISION__ < 5)
+/* Failing MMR Accesses When Stalled by Preceding Memory Read */
+#define ANOMALY_05000198 (__SILICON_REVISION__ < 5)
+/* Current DMA Address Shows Wrong Value During Carry Fix */
+#define ANOMALY_05000199 (__SILICON_REVISION__ < 5)
+/* SPORT TFS and DT Are Incorrectly Driven During Inactive Channels in Certain Conditions */
+#define ANOMALY_05000200 (__SILICON_REVISION__ < 5)
+/* Possible Infinite Stall with Specific Dual-DAG Situation */
+#define ANOMALY_05000202 (__SILICON_REVISION__ < 5)
+/* Incorrect data read with write-through cache and allocate cache lines on reads only mode */
+#define ANOMALY_05000204 (__SILICON_REVISION__ < 5)
+/* Specific sequence that can cause DMA error or DMA stopping */
+#define ANOMALY_05000205 (__SILICON_REVISION__ < 5)
+/* Recovery from "Brown-Out" Condition */
+#define ANOMALY_05000207 (__SILICON_REVISION__ < 5)
+/* VSTAT Status Bit in PLL_STAT Register Is Not Functional */
+#define ANOMALY_05000208 (1)
+/* Speed Path in Computational Unit Affects Certain Instructions */
+#define ANOMALY_05000209 (__SILICON_REVISION__ < 5)
+/* UART TX Interrupt Masked Erroneously */
+#define ANOMALY_05000215 (__SILICON_REVISION__ < 5)
+/* NMI Event at Boot Time Results in Unpredictable State */
+#define ANOMALY_05000219 (__SILICON_REVISION__ < 5)
+/* Data Corruption with Cached External Memory and Non-Cached On-Chip L2 Memory */
+#define ANOMALY_05000220 (__SILICON_REVISION__ < 5)
+/* Incorrect Pulse-Width of UART Start Bit */
+#define ANOMALY_05000225 (__SILICON_REVISION__ < 5)
+/* Scratchpad Memory Bank Reads May Return Incorrect Data */
+#define ANOMALY_05000227 (__SILICON_REVISION__ < 5)
+/* UART Receiver is Less Robust Against Baudrate Differences in Certain Conditions */
+#define ANOMALY_05000230 (__SILICON_REVISION__ < 5)
+/* UART STB Bit Incorrectly Affects Receiver Setting */
+#define ANOMALY_05000231 (__SILICON_REVISION__ < 5)
+/* SPORT data transmit lines are incorrectly driven in multichannel mode */
+#define ANOMALY_05000232 (__SILICON_REVISION__ < 5)
+/* DF Bit in PLL_CTL Register Does Not Respond to Hardware Reset */
+#define ANOMALY_05000242 (__SILICON_REVISION__ < 5)
+/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */
+#define ANOMALY_05000244 (__SILICON_REVISION__ < 5)
+/* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */
+#define ANOMALY_05000245 (__SILICON_REVISION__ < 5)
+/* TESTSET operation forces stall on the other core */
+#define ANOMALY_05000248 (__SILICON_REVISION__ < 5)
+/* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */
+#define ANOMALY_05000250 (__SILICON_REVISION__ > 2 && __SILICON_REVISION__ < 5)
+/* Exception Not Generated for MMR Accesses in Reserved Region */
+#define ANOMALY_05000251 (__SILICON_REVISION__ < 5)
+/* Maximum External Clock Speed for Timers */
+#define ANOMALY_05000253 (__SILICON_REVISION__ < 5)
+/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
+#define ANOMALY_05000254 (__SILICON_REVISION__ > 3)
+/* Interrupt/Exception During Short Hardware Loop May Cause Bad Instruction Fetches */
+#define ANOMALY_05000257 (__SILICON_REVISION__ < 5)
+/* Instruction Cache Is Corrupted When Bits 9 and 12 of the ICPLB Data Registers Differ */
+#define ANOMALY_05000258 (__SILICON_REVISION__ < 5)
+/* ICPLB_STATUS MMR Register May Be Corrupted */
+#define ANOMALY_05000260 (__SILICON_REVISION__ < 5)
+/* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */
+#define ANOMALY_05000261 (__SILICON_REVISION__ < 5)
+/* Stores To Data Cache May Be Lost */
+#define ANOMALY_05000262 (__SILICON_REVISION__ < 5)
+/* Hardware Loop Corrupted When Taking an ICPLB Exception */
+#define ANOMALY_05000263 (__SILICON_REVISION__ < 5)
+/* CSYNC/SSYNC/IDLE Causes Infinite Stall in Penultimate Instruction in Hardware Loop */
+#define ANOMALY_05000264 (__SILICON_REVISION__ < 5)
+/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
+#define ANOMALY_05000265 (__SILICON_REVISION__ < 5)
+/* IMDMA destination IRQ status must be read prior to using IMDMA */
+#define ANOMALY_05000266 (__SILICON_REVISION__ > 3)
+/* IMDMA may corrupt data under certain conditions */
+#define ANOMALY_05000267 (1)
+/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Increase */
+#define ANOMALY_05000269 (1)
+/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */
+#define ANOMALY_05000270 (1)
+/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
+#define ANOMALY_05000272 (1)
+/* Data cache write back to external synchronous memory may be lost */
+#define ANOMALY_05000274 (1)
+/* PPI Timing and Sampling Information Updates */
+#define ANOMALY_05000275 (__SILICON_REVISION__ > 2)
+/* Timing Requirements Change for External Frame Sync PPI Modes with Non-Zero PPI_DELAY */
+#define ANOMALY_05000276 (__SILICON_REVISION__ < 5)
+/* Writes to an I/O data register one SCLK cycle after an edge is detected may clear interrupt */
+#define ANOMALY_05000277 (__SILICON_REVISION__ < 3)
+/* Disabling Peripherals with DMA Running May Cause DMA System Instability */
+#define ANOMALY_05000278 (__SILICON_REVISION__ < 5)
+/* False Hardware Error Exception When ISR Context Is Not Restored */
+#define ANOMALY_05000281 (__SILICON_REVISION__ < 5)
+/* System MMR Write Is Stalled Indefinitely When Killed in a Particular Stage */
+#define ANOMALY_05000283 (1)
+/* A read will receive incorrect data under certain conditions */
+#define ANOMALY_05000287 (__SILICON_REVISION__ < 5)
+/* SPORTs May Receive Bad Data If FIFOs Fill Up */
+#define ANOMALY_05000288 (__SILICON_REVISION__ < 5)
+/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */
+#define ANOMALY_05000301 (1)
+/* SSYNCs After Writes To DMA MMR Registers May Not Be Handled Correctly */
+#define ANOMALY_05000302 (1)
+/* New Feature: Additional Hysteresis on SPORT Input Pins (Not Available On Older Silicon) */
+#define ANOMALY_05000305 (__SILICON_REVISION__ < 5)
+/* SCKELOW Bit Does Not Maintain State Through Hibernate */
+#define ANOMALY_05000307 (__SILICON_REVISION__ < 5)
+/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
+#define ANOMALY_05000310 (1)
+/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
+#define ANOMALY_05000312 (1)
+/* PPI Is Level-Sensitive on First Transfer */
+#define ANOMALY_05000313 (1)
+/* Killed System MMR Write Completes Erroneously On Next System MMR Access */
+#define ANOMALY_05000315 (1)
+/* PF2 Output Remains Asserted After SPI Master Boot */
+#define ANOMALY_05000320 (__SILICON_REVISION__ > 3)
+/* Erroneous GPIO Flag Pin Operations Under Specific Sequences */
+#define ANOMALY_05000323 (1)
+/* SPORT Secondary Receive Channel Not Functional When Word Length Exceeds 16 Bits */
+#define ANOMALY_05000326 (__SILICON_REVISION__ > 3)
+/* New Feature: 24-Bit SPI Boot Mode Support (Not Available On Older Silicon) */
+#define ANOMALY_05000331 (__SILICON_REVISION__ < 5)
+/* New Feature: Slave SPI Boot Mode Supported (Not Available On Older Silicon) */
+#define ANOMALY_05000332 (__SILICON_REVISION__ < 5)
+/* Flag Data Register Writes One SCLK Cycle After Edge Is Detected May Clear Interrupt Status */
+#define ANOMALY_05000333 (__SILICON_REVISION__ < 5)
+/* New Feature: Additional PPI Frame Sync Sampling Options (Not Available on Older Silicon) */
+#define ANOMALY_05000339 (__SILICON_REVISION__ < 5)
+/* Memory DMA FIFO Causes Throughput Degradation on Writes to External Memory */
+#define ANOMALY_05000343 (__SILICON_REVISION__ < 5)
+/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
+#define ANOMALY_05000357 (1)
+/* Conflicting Column Address Widths Causes SDRAM Errors */
+#define ANOMALY_05000362 (1)
+/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
+#define ANOMALY_05000366 (1)
+/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
+#define ANOMALY_05000371 (1)
+
+/* Anomalies that don't exist on this proc */
+#define ANOMALY_05000158 (0)
+#define ANOMALY_05000183 (0)
+#define ANOMALY_05000273 (0)
+#define ANOMALY_05000311 (0)
+
+#endif
diff --git a/include/asm-blackfin/mach-bf561/def_local.h b/include/asm-blackfin/mach-bf561/def_local.h
new file mode 100644
index 0000000..3ddd689
--- /dev/null
+++ b/include/asm-blackfin/mach-bf561/def_local.h
@@ -0,0 +1,10 @@
+#define SWRST SICA_SWRST
+#define SYSCR SICA_SYSCR
+#define bfin_write_SWRST(val) bfin_write_SICA_SWRST(val)
+#define bfin_write_SYSCR(val) bfin_write_SICA_SYSCR(val)
+
+#define WDOG_CNT WDOGA_CNT
+#define WDOG_CTL WDOGA_CTL
+#define bfin_write_WDOG_CNT(val) bfin_write_WDOGA_CNT(val)
+#define bfin_write_WDOG_CTL(val) bfin_write_WDOGA_CTL(val)
+#define bfin_write_WDOG_STAT(val) bfin_write_WDOGA_STAT(val)