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authorWolfgang Denk <wd@pollux.denx.de>2006-03-12 02:55:22 +0100
committerWolfgang Denk <wd@pollux.denx.de>2006-03-12 02:55:22 +0100
commit8e7b703a62783f0e88d3a7e4b1dd1c033bc95ec8 (patch)
tree24c189eb88f7864177be3645e48b44e6e50d6304 /include/asm-blackfin/cpu
parent1264b4050c6f635cc237b5821f924817457ce50c (diff)
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Coding Style cleanup
Diffstat (limited to 'include/asm-blackfin/cpu')
-rw-r--r--include/asm-blackfin/cpu/bf533_irq.h2
-rw-r--r--include/asm-blackfin/cpu/defBF532.h4
-rw-r--r--include/asm-blackfin/cpu/def_LPBlackfin.h6
3 files changed, 6 insertions, 6 deletions
diff --git a/include/asm-blackfin/cpu/bf533_irq.h b/include/asm-blackfin/cpu/bf533_irq.h
index 902308a..9c5230d 100644
--- a/include/asm-blackfin/cpu/bf533_irq.h
+++ b/include/asm-blackfin/cpu/bf533_irq.h
@@ -81,7 +81,7 @@
/* The ABSTRACT IRQ definitions */
-/* The first seven of the following are fixed,
+/* The first seven of the following are fixed,
* the rest you change if you need to
*/
diff --git a/include/asm-blackfin/cpu/defBF532.h b/include/asm-blackfin/cpu/defBF532.h
index c30d5cd..26a5fe6 100644
--- a/include/asm-blackfin/cpu/defBF532.h
+++ b/include/asm-blackfin/cpu/defBF532.h
@@ -30,7 +30,7 @@
/* include all Core registers and bit definitions */
#include <asm/cpu/def_LPBlackfin.h>
-/* Helper macros
+/* Helper macros
* usage:
* P0.H = HI(UART_THR);
* P0.L = LO(UART_THR);
@@ -789,7 +789,7 @@
#define ERR_TYP_P0 0x0E
#define ERR_TYP_P1 0x0F
-/*
+/*
* PROGRAMMABLE FLAG MASKS
*/
diff --git a/include/asm-blackfin/cpu/def_LPBlackfin.h b/include/asm-blackfin/cpu/def_LPBlackfin.h
index 11a6504..9ac78c8 100644
--- a/include/asm-blackfin/cpu/def_LPBlackfin.h
+++ b/include/asm-blackfin/cpu/def_LPBlackfin.h
@@ -21,7 +21,7 @@
#ifndef _DEF_LPBLACKFIN_H
#define _DEF_LPBLACKFIN_H
-/*
+/*
* #if !defined(__ADSPLPBLACKFIN__)
* #warning def_LPBlackfin.h should only be included for 532 compatible chips.
* #endif
@@ -344,9 +344,9 @@
/* ** Masks */
#define ENDM 0x00000001 /* (doesn't really exist) Enable Data Memory L1 */
#define ENDCPLB 0x00000002 /* Enable DCPLB */
-#define ASRAM_BSRAM 0x00000000
+#define ASRAM_BSRAM 0x00000000
#define ACACHE_BSRAM 0x00000008
-#define ACACHE_BCACHE 0x0000000C
+#define ACACHE_BCACHE 0x0000000C
#define DCBS 0x00000010 /* L1 Data Cache Bank Select */
#define PORT_PREF0 0x00001000 /* DAG0 Port Preference */
#define PORT_PREF1 0x00002000 /* DAG1 Port Preference */