diff options
| author | Kim Phillips <kim.phillips@freescale.com> | 2007-04-23 15:58:17 -0500 |
|---|---|---|
| committer | Kim Phillips <kim.phillips@freescale.com> | 2007-04-23 15:58:17 -0500 |
| commit | 396955fed24c301701c83558fc6f7eadd909397b (patch) | |
| tree | e022bf6f768718ce06a29280f3dfa3a0a60f90f3 /include/asm-blackfin/cplb.h | |
| parent | 6fbf261f8df294e589cfadebebe5468e3c0f29e9 (diff) | |
| parent | 14da5f7675bbb427c469e3f45006e027b6e21db9 (diff) | |
| download | u-boot-imx-396955fed24c301701c83558fc6f7eadd909397b.zip u-boot-imx-396955fed24c301701c83558fc6f7eadd909397b.tar.gz u-boot-imx-396955fed24c301701c83558fc6f7eadd909397b.tar.bz2 | |
Merge git://www.denx.de/git/u-boot
Diffstat (limited to 'include/asm-blackfin/cplb.h')
| -rw-r--r-- | include/asm-blackfin/cplb.h | 38 |
1 files changed, 35 insertions, 3 deletions
diff --git a/include/asm-blackfin/cplb.h b/include/asm-blackfin/cplb.h index 7715f64..9d8d9ec 100644 --- a/include/asm-blackfin/cplb.h +++ b/include/asm-blackfin/cplb.h @@ -7,14 +7,15 @@ ************************************************************************/ /* Defines necessary for cplb initialisation routines. */ - #ifndef _CPLB_H #define _CPLB_H +#define CONFIG_BLKFIN_WT + #define CPLB_ENABLE_ICACHE_P 0 #define CPLB_ENABLE_DCACHE_P 1 #define CPLB_ENABLE_DCACHE2_P 2 -#define CPLB_ENABLE_CPLBS_P 3 /* Deprecated!*/ +#define CPLB_ENABLE_CPLBS_P 3 /* Deprecated! */ #define CPLB_ENABLE_ICPLBS_P 4 #define CPLB_ENABLE_DCPLBS_P 5 @@ -45,4 +46,35 @@ #define CPLB_INOCACHE CPLB_USER_RD | CPLB_VALID #define CPLB_IDOCACHE CPLB_INOCACHE | CPLB_L1_CHBL -#endif /* _CPLB_H */ +/* Data Attibutes*/ + +#define SDRAM_IGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID) +#define SDRAM_IKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK) +#define L1_IMEMORY (PAGE_SIZE_1MB | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK) +#define SDRAM_INON_CHBL (PAGE_SIZE_4MB | CPLB_USER_RD | CPLB_VALID) + +/*Use the menuconfig cache policy here - CONFIG_BLKFIN_WT/CONFIG_BLKFIN_WB*/ + +#define ANOMALY_05000158 0x200 + +#ifdef CONFIG_BLKFIN_WB /*Write Back Policy */ +#define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158) +#define SDRAM_DNON_CHBL (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158) +#define SDRAM_DKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_USER_WR | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158) +#define L1_DMEMORY (PAGE_SIZE_4MB | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158) +#define SDRAM_EBIU (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158) + +#else /*Write Through */ +#define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158) +#define SDRAM_DNON_CHBL (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158) +#define SDRAM_DKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158) +#define L1_DMEMORY (PAGE_SIZE_4MB | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158) +#define SDRAM_EBIU (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158) +#endif + +#if defined(CONFIG_BF561) +#define page_descriptor_table_size (CONFIG_MEM_SIZE/4 + 1 + 4) /* SDRAM +L1 + ASYNC_Memory */ +#else +#define page_descriptor_table_size (CONFIG_MEM_SIZE/4 + 2) /* SDRAM + L1 + ASYNC_Memory */ +#endif +#endif /* _CPLB_H */ |