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| author | Dave Liu <daveliu@freescale.com> | 2008-11-21 16:31:22 +0800 |
|---|---|---|
| committer | Andrew Fleming-AFLEMING <afleming@freescale.com> | 2009-01-23 17:03:13 -0600 |
| commit | 80ee3ce6d7fe9441b4352d7cfaf6afc2507b1106 (patch) | |
| tree | 272a979e6e9ed0ae0ab583068657c33793b4355c /include/asm-blackfin/byteorder.h | |
| parent | aca5f018a8386b85469482ed9867e3e29a2437d0 (diff) | |
| download | u-boot-imx-80ee3ce6d7fe9441b4352d7cfaf6afc2507b1106.zip u-boot-imx-80ee3ce6d7fe9441b4352d7cfaf6afc2507b1106.tar.gz u-boot-imx-80ee3ce6d7fe9441b4352d7cfaf6afc2507b1106.tar.bz2 | |
fsl-ddr: update the bit mask for DDR3 controller
According to the latest 8572 UM, the DDR3 controller
is expanding the bit mask, and we use the extend ACTTOPRE
mode when tRAS more than 19 MCLK.
Signed-off-by: Dave Liu <daveliu@freescale.com>
Diffstat (limited to 'include/asm-blackfin/byteorder.h')
0 files changed, 0 insertions, 0 deletions