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| author | Haavard Skinnemoen <haavard.skinnemoen@atmel.com> | 2008-05-19 11:36:28 +0200 |
|---|---|---|
| committer | Haavard Skinnemoen <haavard.skinnemoen@atmel.com> | 2008-05-27 15:27:31 +0200 |
| commit | a23e277c4a3a2bbc42d237aae29da3a8971e757f (patch) | |
| tree | 22e2e0bc2559d38166e1d1844c9a8ac0429b0475 /include/asm-avr32/arch-at32ap700x | |
| parent | 95107b7c028806919630bf02c653aa8f4f867c94 (diff) | |
| download | u-boot-imx-a23e277c4a3a2bbc42d237aae29da3a8971e757f.zip u-boot-imx-a23e277c4a3a2bbc42d237aae29da3a8971e757f.tar.gz u-boot-imx-a23e277c4a3a2bbc42d237aae29da3a8971e757f.tar.bz2 | |
avr32: Rework SDRAM initialization code
This cleans up the SDRAM initialization and related code a bit, and
allows faster booting.
* Add definitions for EBI and internal SRAM to asm/arch/memory-map.h
* Remove memory test from sdram_init() and make caller responsible
for verifying the SDRAM and determining its size.
* Remove base_address member from struct sdram_config (was sdram_info)
* Add data_bits member to struct sdram_config and kill CFG_SDRAM_16BIT
* Add support for a common STK1000 hack: 16MB SDRAM instead of 8.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Diffstat (limited to 'include/asm-avr32/arch-at32ap700x')
| -rw-r--r-- | include/asm-avr32/arch-at32ap700x/memory-map.h | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/include/asm-avr32/arch-at32ap700x/memory-map.h b/include/asm-avr32/arch-at32ap700x/memory-map.h index 5513e88..6592c03 100644 --- a/include/asm-avr32/arch-at32ap700x/memory-map.h +++ b/include/asm-avr32/arch-at32ap700x/memory-map.h @@ -22,6 +22,26 @@ #ifndef __AT32AP7000_MEMORY_MAP_H__ #define __AT32AP7000_MEMORY_MAP_H__ +/* Internal and external memories */ +#define EBI_SRAM_CS0_BASE 0x00000000 +#define EBI_SRAM_CS0_SIZE 0x04000000 +#define EBI_SRAM_CS4_BASE 0x04000000 +#define EBI_SRAM_CS4_SIZE 0x04000000 +#define EBI_SRAM_CS2_BASE 0x08000000 +#define EBI_SRAM_CS2_SIZE 0x04000000 +#define EBI_SRAM_CS3_BASE 0x0c000000 +#define EBI_SRAM_CS3_SIZE 0x04000000 +#define EBI_SRAM_CS1_BASE 0x10000000 +#define EBI_SRAM_CS1_SIZE 0x10000000 +#define EBI_SRAM_CS5_BASE 0x20000000 +#define EBI_SRAM_CS5_SIZE 0x04000000 + +#define EBI_SDRAM_BASE EBI_SRAM_CS1_BASE +#define EBI_SDRAM_SIZE EBI_SRAM_CS1_SIZE + +#define INTERNAL_SRAM_BASE 0x24000000 +#define INTERNAL_SRAM_SIZE 0x00008000 + /* Devices on the High Speed Bus (HSB) */ #define LCDC_BASE 0xFF000000 #define DMAC_BASE 0xFF200000 |