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| author | Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | 2008-10-16 15:01:15 +0200 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2008-10-18 21:54:03 +0200 |
| commit | 6d0f6bcf337c5261c08fabe12982178c2c489d76 (patch) | |
| tree | ae13958ffa9c6b58c2ea97aac07a4ad2f04a350f /include/asm-avr32/arch-at32ap700x/clk.h | |
| parent | 71edc271816ec82cf0550dd6980be2da3cc2ad9e (diff) | |
| download | u-boot-imx-6d0f6bcf337c5261c08fabe12982178c2c489d76.zip u-boot-imx-6d0f6bcf337c5261c08fabe12982178c2c489d76.tar.gz u-boot-imx-6d0f6bcf337c5261c08fabe12982178c2c489d76.tar.bz2 | |
rename CFG_ macros to CONFIG_SYS
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Diffstat (limited to 'include/asm-avr32/arch-at32ap700x/clk.h')
| -rw-r--r-- | include/asm-avr32/arch-at32ap700x/clk.h | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/include/asm-avr32/arch-at32ap700x/clk.h b/include/asm-avr32/arch-at32ap700x/clk.h index e9a4fe4..7817572 100644 --- a/include/asm-avr32/arch-at32ap700x/clk.h +++ b/include/asm-avr32/arch-at32ap700x/clk.h @@ -25,26 +25,26 @@ #include <asm/arch/chip-features.h> #ifdef CONFIG_PLL -#define MAIN_CLK_RATE ((CFG_OSC0_HZ / CFG_PLL0_DIV) * CFG_PLL0_MUL) +#define MAIN_CLK_RATE ((CONFIG_SYS_OSC0_HZ / CONFIG_SYS_PLL0_DIV) * CONFIG_SYS_PLL0_MUL) #else -#define MAIN_CLK_RATE (CFG_OSC0_HZ) +#define MAIN_CLK_RATE (CONFIG_SYS_OSC0_HZ) #endif static inline unsigned long get_cpu_clk_rate(void) { - return MAIN_CLK_RATE >> CFG_CLKDIV_CPU; + return MAIN_CLK_RATE >> CONFIG_SYS_CLKDIV_CPU; } static inline unsigned long get_hsb_clk_rate(void) { - return MAIN_CLK_RATE >> CFG_CLKDIV_HSB; + return MAIN_CLK_RATE >> CONFIG_SYS_CLKDIV_HSB; } static inline unsigned long get_pba_clk_rate(void) { - return MAIN_CLK_RATE >> CFG_CLKDIV_PBA; + return MAIN_CLK_RATE >> CONFIG_SYS_CLKDIV_PBA; } static inline unsigned long get_pbb_clk_rate(void) { - return MAIN_CLK_RATE >> CFG_CLKDIV_PBB; + return MAIN_CLK_RATE >> CONFIG_SYS_CLKDIV_PBB; } /* Accessors for specific devices. More will be added as needed. */ @@ -85,6 +85,6 @@ extern void clk_init(void); extern void gclk_init(void) __attribute__((weak)); /* Board code may need the SDRAM base clock as a compile-time constant */ -#define SDRAMC_BUS_HZ (MAIN_CLK_RATE >> CFG_CLKDIV_HSB) +#define SDRAMC_BUS_HZ (MAIN_CLK_RATE >> CONFIG_SYS_CLKDIV_HSB) #endif /* __ASM_AVR32_ARCH_CLK_H__ */ |