Merge with /home/wd/git/u-boot/master

3 files changed, 439 insertions, 0 deletions

diff --git a/include/asm-avr32/arch-at32ap7000/hmatrix2.h b/include/asm-avr32/arch-at32ap7000/hmatrix2.h
new file mode 100644
index 0000000..e6df4b7
--- /dev/null
+++ b/include/asm-avr32/arch-at32ap7000/hmatrix2.h
@@ -0,0 +1,232 @@
+/*
+ * Register definition for the High-speed Bus Matrix
+ */
+#ifndef __ASM_AVR32_HMATRIX2_H__
+#define __ASM_AVR32_HMATRIX2_H__
+
+/* HMATRIX2 register offsets */
+#define HMATRIX2_MCFG0				0x0000
+#define HMATRIX2_MCFG1				0x0004
+#define HMATRIX2_MCFG2				0x0008
+#define HMATRIX2_MCFG3				0x000c
+#define HMATRIX2_MCFG4				0x0010
+#define HMATRIX2_MCFG5				0x0014
+#define HMATRIX2_MCFG6				0x0018
+#define HMATRIX2_MCFG7				0x001c
+#define HMATRIX2_MCFG8				0x0020
+#define HMATRIX2_MCFG9				0x0024
+#define HMATRIX2_MCFG10				0x0028
+#define HMATRIX2_MCFG11				0x002c
+#define HMATRIX2_MCFG12				0x0030
+#define HMATRIX2_MCFG13				0x0034
+#define HMATRIX2_MCFG14				0x0038
+#define HMATRIX2_MCFG15				0x003c
+#define HMATRIX2_SCFG0				0x0040
+#define HMATRIX2_SCFG1				0x0044
+#define HMATRIX2_SCFG2				0x0048
+#define HMATRIX2_SCFG3				0x004c
+#define HMATRIX2_SCFG4				0x0050
+#define HMATRIX2_SCFG5				0x0054
+#define HMATRIX2_SCFG6				0x0058
+#define HMATRIX2_SCFG7				0x005c
+#define HMATRIX2_SCFG8				0x0060
+#define HMATRIX2_SCFG9				0x0064
+#define HMATRIX2_SCFG10				0x0068
+#define HMATRIX2_SCFG11				0x006c
+#define HMATRIX2_SCFG12				0x0070
+#define HMATRIX2_SCFG13				0x0074
+#define HMATRIX2_SCFG14				0x0078
+#define HMATRIX2_SCFG15				0x007c
+#define HMATRIX2_PRAS0				0x0080
+#define HMATRIX2_PRBS0				0x0084
+#define HMATRIX2_PRAS1				0x0088
+#define HMATRIX2_PRBS1				0x008c
+#define HMATRIX2_PRAS2				0x0090
+#define HMATRIX2_PRBS2				0x0094
+#define HMATRIX2_PRAS3				0x0098
+#define HMATRIX2_PRBS3				0x009c
+#define HMATRIX2_PRAS4				0x00a0
+#define HMATRIX2_PRBS4				0x00a4
+#define HMATRIX2_PRAS5				0x00a8
+#define HMATRIX2_PRBS5				0x00ac
+#define HMATRIX2_PRAS6				0x00b0
+#define HMATRIX2_PRBS6				0x00b4
+#define HMATRIX2_PRAS7				0x00b8
+#define HMATRIX2_PRBS7				0x00bc
+#define HMATRIX2_PRAS8				0x00c0
+#define HMATRIX2_PRBS8				0x00c4
+#define HMATRIX2_PRAS9				0x00c8
+#define HMATRIX2_PRBS9				0x00cc
+#define HMATRIX2_PRAS10				0x00d0
+#define HMATRIX2_PRBS10				0x00d4
+#define HMATRIX2_PRAS11				0x00d8
+#define HMATRIX2_PRBS11				0x00dc
+#define HMATRIX2_PRAS12				0x00e0
+#define HMATRIX2_PRBS12				0x00e4
+#define HMATRIX2_PRAS13				0x00e8
+#define HMATRIX2_PRBS13				0x00ec
+#define HMATRIX2_PRAS14				0x00f0
+#define HMATRIX2_PRBS14				0x00f4
+#define HMATRIX2_PRAS15				0x00f8
+#define HMATRIX2_PRBS15				0x00fc
+#define HMATRIX2_MRCR				0x0100
+#define HMATRIX2_SFR0				0x0110
+#define HMATRIX2_SFR1				0x0114
+#define HMATRIX2_SFR2				0x0118
+#define HMATRIX2_SFR3				0x011c
+#define HMATRIX2_SFR4				0x0120
+#define HMATRIX2_SFR5				0x0124
+#define HMATRIX2_SFR6				0x0128
+#define HMATRIX2_SFR7				0x012c
+#define HMATRIX2_SFR8				0x0130
+#define HMATRIX2_SFR9				0x0134
+#define HMATRIX2_SFR10				0x0138
+#define HMATRIX2_SFR11				0x013c
+#define HMATRIX2_SFR12				0x0140
+#define HMATRIX2_SFR13				0x0144
+#define HMATRIX2_SFR14				0x0148
+#define HMATRIX2_SFR15				0x014c
+#define HMATRIX2_VERSION			0x01fc
+
+/* Bitfields in MCFG0 */
+#define HMATRIX2_ULBT_OFFSET			0
+#define HMATRIX2_ULBT_SIZE			3
+
+/* Bitfields in SCFG0 */
+#define HMATRIX2_SLOT_CYCLE_OFFSET		0
+#define HMATRIX2_SLOT_CYCLE_SIZE		8
+#define HMATRIX2_DEFMSTR_TYPE_OFFSET		16
+#define HMATRIX2_DEFMSTR_TYPE_SIZE		2
+#define HMATRIX2_FIXED_DEFMSTR_OFFSET		18
+#define HMATRIX2_FIXED_DEFMSTR_SIZE		4
+#define HMATRIX2_ARBT_OFFSET			24
+#define HMATRIX2_ARBT_SIZE			2
+
+/* Bitfields in PRAS0 */
+#define HMATRIX2_M0PR_OFFSET			0
+#define HMATRIX2_M0PR_SIZE			4
+#define HMATRIX2_M1PR_OFFSET			4
+#define HMATRIX2_M1PR_SIZE			4
+#define HMATRIX2_M2PR_OFFSET			8
+#define HMATRIX2_M2PR_SIZE			4
+#define HMATRIX2_M3PR_OFFSET			12
+#define HMATRIX2_M3PR_SIZE			4
+#define HMATRIX2_M4PR_OFFSET			16
+#define HMATRIX2_M4PR_SIZE			4
+#define HMATRIX2_M5PR_OFFSET			20
+#define HMATRIX2_M5PR_SIZE			4
+#define HMATRIX2_M6PR_OFFSET			24
+#define HMATRIX2_M6PR_SIZE			4
+#define HMATRIX2_M7PR_OFFSET			28
+#define HMATRIX2_M7PR_SIZE			4
+
+/* Bitfields in PRBS0 */
+#define HMATRIX2_M8PR_OFFSET			0
+#define HMATRIX2_M8PR_SIZE			4
+#define HMATRIX2_M9PR_OFFSET			4
+#define HMATRIX2_M9PR_SIZE			4
+#define HMATRIX2_M10PR_OFFSET			8
+#define HMATRIX2_M10PR_SIZE			4
+#define HMATRIX2_M11PR_OFFSET			12
+#define HMATRIX2_M11PR_SIZE			4
+#define HMATRIX2_M12PR_OFFSET			16
+#define HMATRIX2_M12PR_SIZE			4
+#define HMATRIX2_M13PR_OFFSET			20
+#define HMATRIX2_M13PR_SIZE			4
+#define HMATRIX2_M14PR_OFFSET			24
+#define HMATRIX2_M14PR_SIZE			4
+#define HMATRIX2_M15PR_OFFSET			28
+#define HMATRIX2_M15PR_SIZE			4
+
+/* Bitfields in MRCR */
+#define HMATRIX2_RBC0_OFFSET			0
+#define HMATRIX2_RBC0_SIZE			1
+#define HMATRIX2_RBC1_OFFSET			1
+#define HMATRIX2_RBC1_SIZE			1
+#define HMATRIX2_RBC2_OFFSET			2
+#define HMATRIX2_RBC2_SIZE			1
+#define HMATRIX2_RBC3_OFFSET			3
+#define HMATRIX2_RBC3_SIZE			1
+#define HMATRIX2_RBC4_OFFSET			4
+#define HMATRIX2_RBC4_SIZE			1
+#define HMATRIX2_RBC5_OFFSET			5
+#define HMATRIX2_RBC5_SIZE			1
+#define HMATRIX2_RBC6_OFFSET			6
+#define HMATRIX2_RBC6_SIZE			1
+#define HMATRIX2_RBC7_OFFSET			7
+#define HMATRIX2_RBC7_SIZE			1
+#define HMATRIX2_RBC8_OFFSET			8
+#define HMATRIX2_RBC8_SIZE			1
+#define HMATRIX2_RBC9_OFFSET			9
+#define HMATRIX2_RBC9_SIZE			1
+#define HMATRIX2_RBC10_OFFSET			10
+#define HMATRIX2_RBC10_SIZE			1
+#define HMATRIX2_RBC11_OFFSET			11
+#define HMATRIX2_RBC11_SIZE			1
+#define HMATRIX2_RBC12_OFFSET			12
+#define HMATRIX2_RBC12_SIZE			1
+#define HMATRIX2_RBC13_OFFSET			13
+#define HMATRIX2_RBC13_SIZE			1
+#define HMATRIX2_RBC14_OFFSET			14
+#define HMATRIX2_RBC14_SIZE			1
+#define HMATRIX2_RBC15_OFFSET			15
+#define HMATRIX2_RBC15_SIZE			1
+
+/* Bitfields in SFR0 */
+#define HMATRIX2_SFR_OFFSET			0
+#define HMATRIX2_SFR_SIZE			32
+
+/* Bitfields in SFR4 */
+#define HMATRIX2_CS1A_OFFSET			1
+#define HMATRIX2_CS1A_SIZE			1
+#define HMATRIX2_CS3A_OFFSET			3
+#define HMATRIX2_CS3A_SIZE			1
+#define HMATRIX2_CS4A_OFFSET			4
+#define HMATRIX2_CS4A_SIZE			1
+#define HMATRIX2_CS5A_OFFSET			5
+#define HMATRIX2_CS5A_SIZE			1
+#define HMATRIX2_DBPUC_OFFSET			8
+#define HMATRIX2_DBPUC_SIZE			1
+
+/* Bitfields in VERSION */
+#define HMATRIX2_VERSION_OFFSET			0
+#define HMATRIX2_VERSION_SIZE			12
+#define HMATRIX2_MFN_OFFSET			16
+#define HMATRIX2_MFN_SIZE			3
+
+/* Constants for ULBT */
+#define HMATRIX2_ULBT_INFINITE			0
+#define HMATRIX2_ULBT_SINGLE			1
+#define HMATRIX2_ULBT_FOUR_BEAT			2
+#define HMATRIX2_ULBT_SIXTEEN_BEAT		4
+
+/* Constants for DEFMSTR_TYPE */
+#define HMATRIX2_DEFMSTR_TYPE_NO_DEFAULT	0
+#define HMATRIX2_DEFMSTR_TYPE_LAST_DEFAULT	1
+#define HMATRIX2_DEFMSTR_TYPE_FIXED_DEFAULT	2
+
+/* Constants for ARBT */
+#define HMATRIX2_ARBT_ROUND_ROBIN		0
+#define HMATRIX2_ARBT_FIXED_PRIORITY		1
+
+/* Bit manipulation macros */
+#define HMATRIX2_BIT(name)					\
+	(1 << HMATRIX2_##name##_OFFSET)
+#define HMATRIX2_BF(name,value)					\
+	(((value) & ((1 << HMATRIX2_##name##_SIZE) - 1))	\
+	 << HMATRIX2_##name##_OFFSET)
+#define HMATRIX2_BFEXT(name,value)				\
+	(((value) >> HMATRIX2_##name##_OFFSET)			\
+	 & ((1 << HMATRIX2_##name##_SIZE) - 1))
+#define HMATRIX2_BFINS(name,value,old)				\
+	(((old) & ~(((1 << HMATRIX2_##name##_SIZE) - 1)		\
+		    << HMATRIX2_##name##_OFFSET))		\
+	 | HMATRIX2_BF(name,value))
+
+/* Register access macros */
+#define hmatrix2_readl(port,reg)				\
+	readl((port)->regs + HMATRIX2_##reg)
+#define hmatrix2_writel(port,reg,value)				\
+	writel((value), (port)->regs + HMATRIX2_##reg)
+
+#endif /* __ASM_AVR32_HMATRIX2_H__ */
diff --git a/include/asm-avr32/arch-at32ap7000/memory-map.h b/include/asm-avr32/arch-at32ap7000/memory-map.h
new file mode 100644
index 0000000..8ffe851
--- /dev/null
+++ b/include/asm-avr32/arch-at32ap7000/memory-map.h
@@ -0,0 +1,61 @@
+/*
+ * Copyright (C) 2005-2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __ASM_AVR32_PART_MEMORY_MAP_H__
+#define __ASM_AVR32_PART_MEMORY_MAP_H__
+
+#define AUDIOC_BASE                             0xFFF02800
+#define DAC_BASE                                0xFFF02000
+#define DMAC_BASE                               0xFF200000
+#define ECC_BASE                                0xFFF03C00
+#define HISI_BASE                               0xFFF02C00
+#define HMATRIX_BASE                            0xFFF00800
+#define HSDRAMC_BASE                            0xFFF03800
+#define HSMC_BASE                               0xFFF03400
+#define LCDC_BASE                               0xFF000000
+#define MACB0_BASE                              0xFFF01800
+#define MACB1_BASE                              0xFFF01C00
+#define MMCI_BASE                               0xFFF02400
+#define PIOA_BASE                               0xFFE02800
+#define PIOB_BASE                               0xFFE02C00
+#define PIOC_BASE                               0xFFE03000
+#define PIOD_BASE                               0xFFE03400
+#define PIOE_BASE                               0xFFE03800
+#define PSIF_BASE                               0xFFE03C00
+#define PWM_BASE                                0xFFF01400
+#define SM_BASE                                 0xFFF00000
+#define INTC_BASE				0XFFF00400
+#define SPI0_BASE                               0xFFE00000
+#define SPI1_BASE                               0xFFE00400
+#define SSC0_BASE                               0xFFE01C00
+#define SSC1_BASE                               0xFFE02000
+#define SSC2_BASE                               0xFFE02400
+#define TIMER0_BASE                             0xFFF00C00
+#define TIMER1_BASE                             0xFFF01000
+#define TWI_BASE                                0xFFE00800
+#define USART0_BASE                             0xFFE00C00
+#define USART1_BASE                             0xFFE01000
+#define USART2_BASE                             0xFFE01400
+#define USART3_BASE                             0xFFE01800
+#define USB_FIFO                                0xFF300000
+#define USB_BASE                                0xFFF03000
+
+#endif /* __ASM_AVR32_PART_MEMORY_MAP_H__ */
diff --git a/include/asm-avr32/arch-at32ap7000/platform.h b/include/asm-avr32/arch-at32ap7000/platform.h
new file mode 100644
index 0000000..7590501
--- /dev/null
+++ b/include/asm-avr32/arch-at32ap7000/platform.h
@@ -0,0 +1,146 @@
+/*
+ * Copyright (C) 2005-2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _ASM_AVR32_ARCH_PM_H
+#define _ASM_AVR32_ARCH_PM_H
+
+#include <config.h>
+
+enum clock_domain_id {
+	CLOCK_CPU,
+	CLOCK_HSB,
+	CLOCK_PBA,
+	CLOCK_PBB,
+	NR_CLOCK_DOMAINS,
+};
+
+enum resource_type {
+	RESOURCE_GPIO,
+	RESOURCE_CLOCK,
+};
+
+enum gpio_func {
+	GPIO_FUNC_GPIO,
+	GPIO_FUNC_A,
+	GPIO_FUNC_B,
+};
+
+enum device_id {
+	DEVICE_HEBI,
+	DEVICE_PBA_BRIDGE,
+	DEVICE_PBB_BRIDGE,
+	DEVICE_HRAMC,
+	/* GPIO controllers must be kept together */
+	DEVICE_PIOA,
+	DEVICE_PIOB,
+	DEVICE_PIOC,
+	DEVICE_PIOD,
+	DEVICE_PIOE,
+	DEVICE_SM,
+	DEVICE_INTC,
+	DEVICE_HMATRIX,
+#if defined(CFG_HPDC)
+	DEVICE_HPDC,
+#endif
+#if defined(CFG_MACB0)
+	DEVICE_MACB0,
+#endif
+#if defined(CFG_MACB1)
+	DEVICE_MACB1,
+#endif
+#if defined(CFG_LCDC)
+	DEVICE_LCDC,
+#endif
+#if defined(CFG_USART0)
+	DEVICE_USART0,
+#endif
+#if defined(CFG_USART1)
+	DEVICE_USART1,
+#endif
+#if defined(CFG_USART2)
+	DEVICE_USART2,
+#endif
+#if defined(CFG_USART3)
+	DEVICE_USART3,
+#endif
+#if defined(CFG_MMCI)
+	DEVICE_MMCI,
+#endif
+#if defined(CFG_DMAC)
+	DEVICE_DMAC,
+#endif
+	NR_DEVICES,
+	NO_DEVICE = -1,
+};
+
+struct resource {
+	enum resource_type type;
+	union {
+		struct {
+			unsigned long base;
+		} iomem;
+		struct {
+			unsigned char nr_pins;
+			enum device_id gpio_dev;
+			enum gpio_func func;
+			unsigned short start;
+		} gpio;
+		struct {
+			enum clock_domain_id id;
+			unsigned char index;
+		} clock;
+	} u;
+};
+
+struct device {
+	void *regs;
+	unsigned int nr_resources;
+	const struct resource *resource;
+};
+
+struct clock_domain {
+	unsigned short reg;
+	enum clock_domain_id id;
+	enum device_id bridge;
+};
+
+extern const struct device chip_device[NR_DEVICES];
+extern const struct clock_domain chip_clock[NR_CLOCK_DOMAINS];
+
+/**
+ * Set up PIO, clock management and I/O memory for a device.
+ */
+const struct device *get_device(enum device_id devid);
+void put_device(const struct device *dev);
+
+int gpio_set_func(enum device_id gpio_devid, unsigned int start,
+		  unsigned int nr_pins, enum gpio_func func);
+void gpio_free(enum device_id gpio_devid, unsigned int start,
+	       unsigned int nr_pins);
+
+void pm_init(void);
+int pm_enable_clock(enum clock_domain_id id, unsigned int index);
+void pm_disable_clock(enum clock_domain_id id, unsigned int index);
+unsigned long pm_get_clock_freq(enum clock_domain_id domain);
+
+void cpu_enable_sdram(void);
+
+#endif /* _ASM_AVR32_ARCH_PM_H */