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author | Markus Klotzbuecher <mk@denx.de> | 2007-04-23 13:17:22 +0200 |
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committer | Markus Klotzbuecher <mk@pollux.denx.de> | 2007-04-23 13:17:22 +0200 |
commit | 61ea75aa07838435ec570ac85a2e3fc038844596 (patch) | |
tree | 20135a513c4c9d0bddb2a8ceaf009a8ed5e8bbdf /include/asm-avr32/arch-at32ap7000/clk.h | |
parent | e2fb36a57f364016b973b1db255531e07cfefd52 (diff) | |
parent | 14da5f7675bbb427c469e3f45006e027b6e21db9 (diff) | |
download | u-boot-imx-61ea75aa07838435ec570ac85a2e3fc038844596.zip u-boot-imx-61ea75aa07838435ec570ac85a2e3fc038844596.tar.gz u-boot-imx-61ea75aa07838435ec570ac85a2e3fc038844596.tar.bz2 |
Merge with git://www.denx.de/git/u-boot.git
Diffstat (limited to 'include/asm-avr32/arch-at32ap7000/clk.h')
-rw-r--r-- | include/asm-avr32/arch-at32ap7000/clk.h | 70 |
1 files changed, 70 insertions, 0 deletions
diff --git a/include/asm-avr32/arch-at32ap7000/clk.h b/include/asm-avr32/arch-at32ap7000/clk.h new file mode 100644 index 0000000..7e20d97 --- /dev/null +++ b/include/asm-avr32/arch-at32ap7000/clk.h @@ -0,0 +1,70 @@ +/* + * Copyright (C) 2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_AVR32_ARCH_CLK_H__ +#define __ASM_AVR32_ARCH_CLK_H__ + +#ifdef CONFIG_PLL +#define MAIN_CLK_RATE ((CFG_OSC0_HZ / CFG_PLL0_DIV) * CFG_PLL0_MUL) +#else +#define MAIN_CLK_RATE (CFG_OSC0_HZ) +#endif + +static inline unsigned long get_cpu_clk_rate(void) +{ + return MAIN_CLK_RATE >> CFG_CLKDIV_CPU; +} +static inline unsigned long get_hsb_clk_rate(void) +{ + return MAIN_CLK_RATE >> CFG_CLKDIV_HSB; +} +static inline unsigned long get_pba_clk_rate(void) +{ + return MAIN_CLK_RATE >> CFG_CLKDIV_PBA; +} +static inline unsigned long get_pbb_clk_rate(void) +{ + return MAIN_CLK_RATE >> CFG_CLKDIV_PBB; +} + +/* Accessors for specific devices. More will be added as needed. */ +static inline unsigned long get_sdram_clk_rate(void) +{ + return get_hsb_clk_rate(); +} +static inline unsigned long get_usart_clk_rate(unsigned int dev_id) +{ + return get_pba_clk_rate(); +} +static inline unsigned long get_macb_pclk_rate(unsigned int dev_id) +{ + return get_pbb_clk_rate(); +} +static inline unsigned long get_macb_hclk_rate(unsigned int dev_id) +{ + return get_hsb_clk_rate(); +} +static inline unsigned long get_mci_clk_rate(void) +{ + return get_pbb_clk_rate(); +} + +#endif /* __ASM_AVR32_ARCH_CLK_H__ */ |