Merge git://www.denx.de/git/u-boot

Conflicts:

	board/tqm5200/tqm5200.c

5 files changed, 86 insertions, 6 deletions

diff --git a/include/asm-arm/arch-arm1136/mux.h b/include/asm-arm/arch-arm1136/mux.h
index 67c8419..4fdb9c6 100644
--- a/include/asm-arm/arch-arm1136/mux.h
+++ b/include/asm-arm/arch-arm1136/mux.h
@@ -28,6 +28,7 @@ typedef  unsigned int uint32;
 void muxSetupSDRC(void);
 void muxSetupGPMC(void);
 void muxSetupUsb0(void);
+void muxSetupUsbHost(void);
 void muxSetupUart3(void);
 void muxSetupI2C1(void);
 void muxSetupUART1(void);
@@ -53,6 +54,10 @@ void muxSetupHDQ(void);
 #define CONTROL_PADCONF_GPMC_NCS0_BYTE1	((volatile unsigned char *)0x4800008D)
 #define CONTROL_PADCONF_GPMC_NCS0_BYTE2	((volatile unsigned char *)0x4800008E)
 #define CONTROL_PADCONF_GPMC_NCS0_BYTE3	((volatile unsigned char *)0x4800008F)
+#define CONTROL_PADCONF_GPMC_NCS0_BYTE4	(0x48000090)
+#define CONTROL_PADCONF_GPMC_NCS0_BYTE5	(0x48000091)
+#define CONTROL_PADCONF_GPMC_NCS0_BYTE6	(0x48000092)
+#define CONTROL_PADCONF_GPMC_NCS0_BYTE7	(0x48000093)
 
 /* Pin Muxing registers used for SDRC */
 #define CONTROL_PADCONF_SDRC_NCS0_BYTE0 ((volatile unsigned char *)0x480000A0)
@@ -70,6 +75,7 @@ void muxSetupHDQ(void);
 #define CONTROL_PADCONF_SPI1_SIMO       ((volatile unsigned char *)0x48000100)
 #define CONTROL_PADCONF_SPI1_SOMI       ((volatile unsigned char *)0x48000101)
 #define CONTROL_PADCONF_SPI1_NCS0       ((volatile unsigned char *)0x48000102)
+#define CONTROL_PADCONF_SPI1_NCS1       (0x48000103)
 
 #define CONTROL_PADCONF_MCBSP1_FSR      ((volatile unsigned char *)0x4800010B)
 
@@ -151,8 +157,20 @@ void muxSetupHDQ(void);
 #define CONTROL_PADCONF_USB0_SE0		((volatile uint8 *)0x48000122)
 #define CONTROL_PADCONF_USB0_DAT		((volatile uint8 *)0x48000123)
 
+/* Pin Muxing registres used for USB1. */
+#define CONTROL_PADCONF_USB1_RCV	(0x480000EB)
+#define CONTROL_PADCONF_USB1_TXEN	(0x480000EC)
+
 /* Pin Muxing registers used for UART3/IRDA */
 #define CONTROL_PADCONF_UART3_TX_IRTX	((volatile uint8 *)0x48000118)
 #define CONTROL_PADCONF_UART3_RX_IRRX	((volatile uint8 *)0x48000119)
 
+/* Pin Muxing registers used for GPIO */
+#define CONTROL_PADCONF_GPIO69		(0x480000ED)
+#define CONTROL_PADCONF_GPIO70		(0x480000EE)
+#define CONTROL_PADCONF_GPIO102		(0x48000116)
+#define CONTROL_PADCONF_GPIO103		(0x48000117)
+#define CONTROL_PADCONF_GPIO104		(0x48000118)
+#define CONTROL_PADCONF_GPIO105		(0x48000119)
+
 #endif
diff --git a/include/asm-arm/arch-arm1136/omap2420.h b/include/asm-arm/arch-arm1136/omap2420.h
index d833035..0c11bec 100644
--- a/include/asm-arm/arch-arm1136/omap2420.h
+++ b/include/asm-arm/arch-arm1136/omap2420.h
@@ -77,6 +77,20 @@
 #define GPMC_CONFIG5_1        (OMAP2420_GPMC_BASE+0xA0)
 #define GPMC_CONFIG6_1        (OMAP2420_GPMC_BASE+0xA4)
 #define GPMC_CONFIG7_1	      (OMAP2420_GPMC_BASE+0xA8)
+#define GPMC_CONFIG1_2        (OMAP2420_GPMC_BASE+0xC0)
+#define GPMC_CONFIG2_2        (OMAP2420_GPMC_BASE+0xC4)
+#define GPMC_CONFIG3_2        (OMAP2420_GPMC_BASE+0xC8)
+#define GPMC_CONFIG4_2        (OMAP2420_GPMC_BASE+0xCC)
+#define GPMC_CONFIG5_2        (OMAP2420_GPMC_BASE+0xD0)
+#define GPMC_CONFIG6_2        (OMAP2420_GPMC_BASE+0xD4)
+#define GPMC_CONFIG7_2        (OMAP2420_GPMC_BASE+0xD8)
+#define GPMC_CONFIG1_3        (OMAP2420_GPMC_BASE+0xF0)
+#define GPMC_CONFIG2_3        (OMAP2420_GPMC_BASE+0xF4)
+#define GPMC_CONFIG3_3        (OMAP2420_GPMC_BASE+0xF8)
+#define GPMC_CONFIG4_3        (OMAP2420_GPMC_BASE+0xFC)
+#define GPMC_CONFIG5_3        (OMAP2420_GPMC_BASE+0x100)
+#define GPMC_CONFIG6_3        (OMAP2420_GPMC_BASE+0x104)
+#define GPMC_CONFIG7_3	      (OMAP2420_GPMC_BASE+0x108)
 
 /* SMS */
 #define OMAP2420_SMS_BASE 0x68008000
@@ -209,13 +223,24 @@
 #define SRAM_OFFSET2          0x0000F800
 #define SRAM_VECT_CODE       (SRAM_OFFSET0|SRAM_OFFSET1|SRAM_OFFSET2)
 
-#define LOW_LEVEL_SRAM_STACK  0x4020FFFC
-
-#define PERIFERAL_PORT_BASE   0x480FE003
-
 /* FPGA on Debug board.*/
 #define ETH_CONTROL_REG       (H4_CS1_BASE+0x30b)
 #define LAN_RESET_REGISTER    (H4_CS1_BASE+0x1c)
 #endif  /* endif CONFIG_2420H4 */
 
+#if defined(CONFIG_APOLLON)
+#define APOLLON_CS0_BASE	0x00000000	/* OneNAND */
+#define APOLLON_CS1_BASE	0x08000000	/* ethernet */
+#define APOLLON_CS2_BASE	0x10000000	/* OneNAND */
+#define APOLLON_CS3_BASE	0x18000000	/* NOR */
+
+#define ETH_CONTROL_REG		(APOLLON_CS1_BASE + 0x30b)
+#define LAN_RESET_REGISTER	(APOLLON_CS1_BASE + 0x1c)
+#endif	/* endif CONFIG_APOLLON */
+
+/* Common */
+#define LOW_LEVEL_SRAM_STACK  0x4020FFFC
+
+#define PERIFERAL_PORT_BASE   0x480FE003
+
 #endif
diff --git a/include/asm-arm/arch-at91rm9200/hardware.h b/include/asm-arm/arch-at91rm9200/hardware.h
index 8bb0c47..b868e38 100644
--- a/include/asm-arm/arch-at91rm9200/hardware.h
+++ b/include/asm-arm/arch-at91rm9200/hardware.h
@@ -24,8 +24,6 @@
 
 #ifndef __ASSEMBLY__
 #include "AT91RM9200.h"
-#else
-#include "AT91RM9200_inc.h"
 #endif
 
 /* Virtual and Physical base address for system peripherals */
diff --git a/include/asm-arm/io.h b/include/asm-arm/io.h
index 47c18e7..029b7f9 100644
--- a/include/asm-arm/io.h
+++ b/include/asm-arm/io.h
@@ -34,6 +34,32 @@ static inline void sync(void)
 }
 
 /*
+ * Given a physical address and a length, return a virtual address
+ * that can be used to access the memory range with the caching
+ * properties specified by "flags".
+ */
+typedef unsigned long phys_addr_t;
+
+#define MAP_NOCACHE	(0)
+#define MAP_WRCOMBINE	(0)
+#define MAP_WRBACK	(0)
+#define MAP_WRTHROUGH	(0)
+
+static inline void *
+map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)
+{
+	return (void *)paddr;
+}
+
+/*
+ * Take down a mapping set up by map_physmem().
+ */
+static inline void unmap_physmem(void *vaddr, unsigned long flags)
+{
+
+}
+
+/*
  * Generic virtual read/write.  Note that we don't support half-word
  * read/writes.  We define __arch_*[bl] here, and leave __arch_*w
  * to the architecture specific code.
diff --git a/include/asm-arm/mach-types.h b/include/asm-arm/mach-types.h
index f6a5b4f..ab19047 100644
--- a/include/asm-arm/mach-types.h
+++ b/include/asm-arm/mach-types.h
@@ -737,6 +737,7 @@ extern unsigned int __machine_arch_type;
 #define MACH_TYPE_CB3RUFC              726
 #define MACH_TYPE_MP2USB               727
 #define MACH_TYPE_AT91SAM9261EK        848
+#define MACH_TYPE_OMAP_APOLLON         919
 #define MACH_TYPE_PDNB3               1002
 #define MACH_TYPE_AT91SAM9260EK       1099
 #define MACH_TYPE_AT91RM9200DF        1119
@@ -6826,6 +6827,18 @@ extern unsigned int __machine_arch_type;
 # define machine_is_omap_h4()	(0)
 #endif
 
+#ifdef CONFIG_MACH_OMAP_APOLLON
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_OMAP_APOLLON
+# endif
+# define machine_is_omap_apollon()	(machine_arch_type == MACH_TYPE_OMAP_APOLLON)
+#else
+# define machine_is_omap_apollon()	(0)
+#endif
+
 #ifdef CONFIG_MACH_N10
 # ifdef machine_arch_type
 #  undef machine_arch_type