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authorMarkus Klotzbücher <Markus Klotzbümk@pollux.denx.de>2006-03-06 15:04:25 +0100
committerMarkus Klotzbücher <mk@pollux.denx.de>2006-03-06 15:04:25 +0100
commit43638c674a1bc57eef41439e87c281269a08cb16 (patch)
treec42d1e3340add6c4b4099ea59b603ecffbe0430d /include/asm-arm
parentf9e029184be5ef550d05262e0f150d31fb09d19b (diff)
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Cleanup of NAND support of delta board using the Monahans Data Flash
Controller.
Diffstat (limited to 'include/asm-arm')
-rw-r--r--include/asm-arm/arch-pxa/pxa-regs.h17
1 files changed, 17 insertions, 0 deletions
diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h
index 6236405..5d36b84 100644
--- a/include/asm-arm/arch-pxa/pxa-regs.h
+++ b/include/asm-arm/arch-pxa/pxa-regs.h
@@ -880,6 +880,8 @@ typedef void (*ExcpHndlr) (void) ;
#define OMCR9 __REG(0x40A000D4) /* OS Match Control Register 9 */
#define OMCR10 __REG(0x40A000D8) /* OS Match Control Register 10 */
#define OMCR11 __REG(0x40A000DC) /* OS Match Control Register 11 */
+
+#define OSCR_CLK_FREQ 3.250 /* MHz */
#endif /* CONFIG_CPU_MONAHANS */
#define OSSR_M4 (1 << 4) /* Match status channel 4 */
@@ -2132,6 +2134,21 @@ typedef void (*ExcpHndlr) (void) ;
#define MCIO(s) MCIO0
#define MECR_CIT (1 << 1)/* Card Is There: 0 -> no card, 1 -> card inserted */
+/* Maximum values for NAND Interface Timing Registers in DFC clock
+ * periods */
+#define DFC_MAX_tCH 7
+#define DFC_MAX_tCS 7
+#define DFC_MAX_tWH 7
+#define DFC_MAX_tWP 7
+#define DFC_MAX_tRH 7
+#define DFC_MAX_tRP 15
+#define DFC_MAX_tR 65535
+#define DFC_MAX_tWHR 15
+#define DFC_MAX_tAR 15
+
+#define DFC_CLOCK 104 /* DFC Clock is 104 MHz */
+#define DFC_CLK_PER_US DFC_CLOCK/1000 /* clock period in ns */
+
#else /* CONFIG_CPU_MONAHANS */
#define MEMC_BASE __REG(0x48000000) /* Base of Memory Controller */