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| author | Danny Nold <dannynold@freescale.com> | 2012-05-30 09:10:39 -0500 |
|---|---|---|
| committer | Danny Nold <dannynold@freescale.com> | 2012-05-30 09:10:39 -0500 |
| commit | 41e9b04376a74ee74133368d9f5b18ee033efa55 (patch) | |
| tree | dbe569f42a85f0733a17469fad2f216e963b8550 /include/asm-arm | |
| parent | 75752c1cbe95c9f6241f3054b6435312d6708a38 (diff) | |
| download | u-boot-imx-41e9b04376a74ee74133368d9f5b18ee033efa55.zip u-boot-imx-41e9b04376a74ee74133368d9f5b18ee033efa55.tar.gz u-boot-imx-41e9b04376a74ee74133368d9f5b18ee033efa55.tar.bz2 | |
ENGR00211117 - U-Boot: Add EPDC splash screen for MX 6DL/S platforms
- EPDC Splash support for MX6DL/S Sabre SD
- EPDC Splash support for MX6DL/S ARM2
- Currently, splash screen consists of a simple black border
around a white screen. Done this way to save in memory footprint.
Signed-off-by: Danny Nold <dannynold@freescale.com>
Diffstat (limited to 'include/asm-arm')
| -rw-r--r-- | include/asm-arm/arch-mx6/mx6.h | 13 |
1 files changed, 7 insertions, 6 deletions
diff --git a/include/asm-arm/arch-mx6/mx6.h b/include/asm-arm/arch-mx6/mx6.h index 26dd0b3..d03adc9 100644 --- a/include/asm-arm/arch-mx6/mx6.h +++ b/include/asm-arm/arch-mx6/mx6.h @@ -266,15 +266,15 @@ #define CSI_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000) #define SIPIX_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000) #define SDMA_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000) -#define EPXP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x70000) -#define EPDC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x74000) -#define ELCDIF_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x78000) -#define DCP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x7C000) #else #define DCIC1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000) #define DCIC2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000) #define DMA_REQ_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000) #endif +#define EPXP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x70000) +#define EPDC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x74000) +#define ELCDIF_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x78000) +#define DCP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x7C000) /* ATZ#2- On Platform */ #define AIPS2_ON_BASE_ADDR (ATZ2_BASE_ADDR + 0x7C000) @@ -697,8 +697,9 @@ #define CLKCTL_CCGR7 0x84 #define CLKCTL_CMEOR 0x88 -#define ANATOP_USB1 0x10 -#define ANATOP_USB2 0x20 +#define ANATOP_USB1 0x10 +#define ANATOP_USB2 0x20 +#define ANATOP_PLL_VIDEO 0xA0 #define CHIP_TYPE_DQ 0x63000 #define CHIP_TYPE_DL 0x61000 |