ENGR00119171: ubifs support for android recovery mode.

ubifs support for android recovery mode.

Signed-off-by: Terry Lv <r65388@freescale.com>

2 files changed, 44 insertions, 67 deletions

diff --git a/include/asm-arm/bitops.h b/include/asm-arm/bitops.h
index 4b8bab2..8eeada5 100644
--- a/include/asm-arm/bitops.h
+++ b/include/asm-arm/bitops.h
@@ -17,6 +17,8 @@
 
 #ifdef __KERNEL__
 
+#include <asm/proc/system.h>
+
 #define smp_mb__before_clear_bit()	do { } while (0)
 #define smp_mb__after_clear_bit()	do { } while (0)
 
@@ -25,59 +27,72 @@
  */
 extern void set_bit(int nr, volatile void * addr);
 
-static inline void __set_bit(int nr, volatile void *addr)
-{
-	((unsigned char *) addr)[nr >> 3] |= (1U << (nr & 7));
-}
-
 extern void clear_bit(int nr, volatile void * addr);
 
-static inline void __clear_bit(int nr, volatile void *addr)
-{
-	((unsigned char *) addr)[nr >> 3] &= ~(1U << (nr & 7));
-}
-
 extern void change_bit(int nr, volatile void * addr);
 
 static inline void __change_bit(int nr, volatile void *addr)
 {
-	((unsigned char *) addr)[nr >> 3] ^= (1U << (nr & 7));
-}
+	unsigned long mask = BIT_MASK(nr);
+	unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
 
-extern int test_and_set_bit(int nr, volatile void * addr);
+	*p ^= mask;
+}
 
 static inline int __test_and_set_bit(int nr, volatile void *addr)
 {
-	unsigned int mask = 1 << (nr & 7);
-	unsigned int oldval;
+	unsigned long mask = BIT_MASK(nr);
+	unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
+	unsigned long old = *p;
 
-	oldval = ((unsigned char *) addr)[nr >> 3];
-	((unsigned char *) addr)[nr >> 3] = oldval | mask;
-	return oldval & mask;
+	*p = old | mask;
+	return (old & mask) != 0;
 }
 
-extern int test_and_clear_bit(int nr, volatile void * addr);
+static inline int test_and_set_bit(int nr, volatile void *addr)
+{
+	unsigned long flags;
+	int out;
+
+	local_irq_save(flags);
+	out = __test_and_set_bit(nr, addr);
+	local_irq_restore(flags);
+
+	return out;
+}
 
 static inline int __test_and_clear_bit(int nr, volatile void *addr)
 {
-	unsigned int mask = 1 << (nr & 7);
-	unsigned int oldval;
+	unsigned long mask = BIT_MASK(nr);
+	unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
+	unsigned long old = *p;
 
-	oldval = ((unsigned char *) addr)[nr >> 3];
-	((unsigned char *) addr)[nr >> 3] = oldval & ~mask;
-	return oldval & mask;
+	*p = old & ~mask;
+	return (old & mask) != 0;
+}
+
+static inline int test_and_clear_bit(int nr, volatile void *addr)
+{
+	unsigned long flags;
+	int out;
+
+	local_irq_save(flags);
+	out = __test_and_clear_bit(nr, addr);
+	local_irq_restore(flags);
+
+	return out;
 }
 
 extern int test_and_change_bit(int nr, volatile void * addr);
 
 static inline int __test_and_change_bit(int nr, volatile void *addr)
 {
-	unsigned int mask = 1 << (nr & 7);
-	unsigned int oldval;
+	unsigned long mask = BIT_MASK(nr);
+	unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
+	unsigned long old = *p;
 
-	oldval = ((unsigned char *) addr)[nr >> 3];
-	((unsigned char *) addr)[nr >> 3] = oldval ^ mask;
-	return oldval & mask;
+	*p = old ^ mask;
+	return (old & mask) != 0;
 }
 
 extern int find_first_zero_bit(void * addr, unsigned size);
@@ -110,14 +125,6 @@ static inline unsigned long ffz(unsigned long word)
 }
 
 /*
- * ffs: find first bit set. This is defined the same way as
- * the libc and compiler builtin ffs routines, therefore
- * differs in spirit from the above ffz (man ffs).
- */
-
-#define ffs(x) generic_ffs(x)
-
-/*
  * hweightN: returns the hamming weight (i.e. the number
  * of bits set) of a N-bit word
  */
diff --git a/include/asm-arm/proc-armv/system.h b/include/asm-arm/proc-armv/system.h
index e7b0fe6..b4cfa68 100644
--- a/include/asm-arm/proc-armv/system.h
+++ b/include/asm-arm/proc-armv/system.h
@@ -12,36 +12,6 @@
 
 #include <linux/config.h>
 
-#define set_cr(x)					\
-	__asm__ __volatile__(				\
-	"mcr	p15, 0, %0, c1, c0	@ set CR"	\
-	: : "r" (x))
-
-#define CR_M	(1 << 0)	/* MMU enable				*/
-#define CR_A	(1 << 1)	/* Alignment abort enable		*/
-#define CR_C	(1 << 2)	/* Dcache enable			*/
-#define CR_W	(1 << 3)	/* Write buffer enable			*/
-#define CR_P	(1 << 4)	/* 32-bit exception handler		*/
-#define CR_D	(1 << 5)	/* 32-bit data address range		*/
-#define CR_L	(1 << 6)	/* Implementation defined		*/
-#define CD_B	(1 << 7)	/* Big endian				*/
-#define CR_S	(1 << 8)	/* System MMU protection		*/
-#define CD_R	(1 << 9)	/* ROM MMU protection			*/
-#define CR_F	(1 << 10)	/* Implementation defined		*/
-#define CR_Z	(1 << 11)	/* Implementation defined		*/
-#define CR_I	(1 << 12)	/* Icache enable			*/
-#define CR_V	(1 << 13)	/* Vectors relocated to 0xffff0000	*/
-#define CR_RR	(1 << 14)	/* Round Robin cache replacement	*/
-
-extern unsigned long cr_no_alignment;	/* defined in entry-armv.S */
-extern unsigned long cr_alignment;	/* defined in entry-armv.S */
-
-#if __LINUX_ARM_ARCH__ >= 4
-#define vectors_base()	((cr_alignment & CR_V) ? 0xffff0000 : 0)
-#else
-#define vectors_base()	(0)
-#endif
-
 /*
  * Save the current interrupt enable state & disable IRQs
  */