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| author | Terry Lv <r65388@freescale.com> | 2010-02-24 18:34:13 +0800 |
|---|---|---|
| committer | Terry Lv <r65388@freescale.com> | 2010-03-04 14:55:00 +0800 |
| commit | bd6578e46d1ba93ffe6e00147704d7d18c7e5573 (patch) | |
| tree | 424b9a30a2e791ff267b2aaa27d0d52186693b8e /include/asm-arm/mmu.h | |
| parent | 871825c1148b233fb562c09204700b59fcd28b67 (diff) | |
| download | u-boot-imx-bd6578e46d1ba93ffe6e00147704d7d18c7e5573.zip u-boot-imx-bd6578e46d1ba93ffe6e00147704d7d18c7e5573.tar.gz u-boot-imx-bd6578e46d1ba93ffe6e00147704d7d18c7e5573.tar.bz2 | |
ENGR00120520: Enable MMU for mx51 and mx35
MMU enable code is missed in mx51 and mx35 u-boot.
So add these codes.
Signed-off-by: Terry Lv <r65388@freescale.com>
Diffstat (limited to 'include/asm-arm/mmu.h')
| -rw-r--r-- | include/asm-arm/mmu.h | 41 |
1 files changed, 40 insertions, 1 deletions
diff --git a/include/asm-arm/mmu.h b/include/asm-arm/mmu.h index 668dfc9..f1b7574 100644 --- a/include/asm-arm/mmu.h +++ b/include/asm-arm/mmu.h @@ -1,5 +1,5 @@ /* - * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. */ /* @@ -14,6 +14,7 @@ #ifndef __ASM_MMU_H #define __ASM_MMU_H +#include <asm/system.h> #define MMU_L1_TYPE 0x03 /* Descriptor type */ #define MMU_L1_TYPE_Fault 0x00 /* Invalid */ @@ -76,4 +77,42 @@ #define MMU_Control_Z 0x800 /* Enable branch predicion */ #define MMU_Control_RR 0x4000 /* Select non-random cache replacement */ +#ifdef CONFIG_ARCH_MMU + +#define MMU_ON() \ + { \ + unsigned long cr = 0; \ + asm volatile ("mrc p15, 0, %0, c1, c0;" : "=r"(cr) : /*:*/); \ + cr |= (CR_M | CR_A | CR_C | CR_Z); \ + asm volatile ("mcr p15, 0, %0, c1, c0;" : : "r"(cr) /*:*/); \ + /* Clean instruction pipeline */ \ + asm volatile ( \ + "b skip;" \ + "nop;" \ + "nop;" \ + "nop;" \ + "skip:" \ + ); \ + } + +#define MMU_OFF() \ + { \ + unsigned long cr = 0; \ + asm volatile ("mrc p15, 0, %0, c1, c0;" : "=r"(cr) /*: :*/); \ + cr &= (~(CR_M | CR_A | CR_C | CR_I)); \ + asm volatile ("mcr p15, 0, %0, c1, c0;" : : "r"(cr) /*:*/); \ + asm volatile ( \ + "nop;" /* flush i+d-TLBs */ \ + "nop;" /* flush i+d-TLBs */ \ + "nop;" /* flush i+d-TLBs */ \ + ); \ + } + +#else + +#define MMU_ON() +#define MMU_OFF() + +#endif + #endif |