diff options
| author | Minkyu Kang <mk7.kang@samsung.com> | 2009-10-01 17:20:01 +0900 |
|---|---|---|
| committer | Tom Rix <Tom.Rix@windriver.com> | 2009-10-13 21:13:55 -0500 |
| commit | 399e5ae0d0b2eb4663fc5784201968c07d45afac (patch) | |
| tree | 9c88ca02e6f2d4432a025b05ad2cb83bf3ba3785 /include/asm-arm/arch-s5pc1xx/pwm.h | |
| parent | a380279b2abe130c2d3d2c8de36f8ff98bc6b3b0 (diff) | |
| download | u-boot-imx-399e5ae0d0b2eb4663fc5784201968c07d45afac.zip u-boot-imx-399e5ae0d0b2eb4663fc5784201968c07d45afac.tar.gz u-boot-imx-399e5ae0d0b2eb4663fc5784201968c07d45afac.tar.bz2 | |
s5pc1xx: support Samsung s5pc1xx SoC
This patch adds support for the Samsung s5pc100 and s5pc110
SoCs. The s5pc1xx SoC is an ARM Cortex A8 processor.
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: HeungJun, Kim <riverful.kim@samsung.com>
Diffstat (limited to 'include/asm-arm/arch-s5pc1xx/pwm.h')
| -rw-r--r-- | include/asm-arm/arch-s5pc1xx/pwm.h | 59 |
1 files changed, 59 insertions, 0 deletions
diff --git a/include/asm-arm/arch-s5pc1xx/pwm.h b/include/asm-arm/arch-s5pc1xx/pwm.h new file mode 100644 index 0000000..53c23cd --- /dev/null +++ b/include/asm-arm/arch-s5pc1xx/pwm.h @@ -0,0 +1,59 @@ +/* + * Copyright (C) 2009 Samsung Electronics + * Kyungmin Park <kyungmin.park@samsung.com> + * Minkyu Kang <mk7.kang@samsung.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_ARM_ARCH_PWM_H_ +#define __ASM_ARM_ARCH_PWM_H_ + +/* PWM timer addressing */ +#define S5PC100_TIMER_BASE S5PC100_PWMTIMER_BASE +#define S5PC110_TIMER_BASE S5PC110_PWMTIMER_BASE + +/* Interval mode(Auto Reload) of PWM Timer 4 */ +#define S5PC1XX_TCON4_AUTO_RELOAD (1 << 22) +/* Update TCNTB4 */ +#define S5PC1XX_TCON4_UPDATE (1 << 21) +/* start bit of PWM Timer 4 */ +#define S5PC1XX_TCON4_START (1 << 20) + +#ifndef __ASSEMBLY__ +struct s5pc1xx_timer { + unsigned long tcfg0; + unsigned long tcfg1; + unsigned long tcon; + unsigned long tcntb0; + unsigned long tcmpb0; + unsigned long tcnto0; + unsigned long tcntb1; + unsigned long tcmpb1; + unsigned long tcnto1; + unsigned long tcntb2; + unsigned long tcmpb2; + unsigned long tcnto2; + unsigned long tcntb3; + unsigned long res1; + unsigned long tcnto3; + unsigned long tcntb4; + unsigned long tcnto4; + unsigned long tintcstat; +}; +#endif /* __ASSEMBLY__ */ + +#endif |