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authorMarkus Klotzbücher <Markus Klotzbümk@pollux.(none)>2006-02-22 00:06:01 +0100
committerMarkus Klotzbücher <mk@pollux.(none)>2006-02-22 00:06:01 +0100
commit48b6242aa1a5c8ef5f08abf30ebf9a49e3d95bd7 (patch)
treef2ede9e49ec15b21e06d0e38a991c7f340fc0a3f /include/asm-arm/arch-pxa
parent4f7a0e36713d93591812bfd424002c3aa5337c56 (diff)
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SDRAM seems to be working on delta board, though u-boot doesn't start yet.
Diffstat (limited to 'include/asm-arm/arch-pxa')
-rw-r--r--include/asm-arm/arch-pxa/pxa-regs.h25
1 files changed, 25 insertions, 0 deletions
diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h
index 235a365..44532c9 100644
--- a/include/asm-arm/arch-pxa/pxa-regs.h
+++ b/include/asm-arm/arch-pxa/pxa-regs.h
@@ -1994,6 +1994,31 @@ typedef void (*ExcpHndlr) (void) ;
#define PAD_SCLK __REG_2(0x4810012C)
#define TAI __REG_2(0x48100F00) /* TAI Tavor Address Isolation Register */
+/* Some frequently used bits */
+#define MDCNFG_DMAP 0x80000000 /* SDRAM 1GB Memory Map Enable */
+#define MDCNFG_DMCEN 0x40000000 /* Enable Dynamic Memory Controller */
+#define MDCNFG_HWFREQ 0x20000000 /* Hardware Frequency Change Calibration */
+#define MDCNFG_DTYPE 0x400 /* SDRAM Type: 1=DDR SDRAM */
+
+#define MDCNFG_DTC_0 0x0 /* Timing Category of SDRAM */
+#define MDCNFG_DTC_1 0x100
+#define MDCNFG_DTC_2 0x200
+#define MDCNFG_DTC_3 0x300
+
+#define MDCNFG_DRAC_12 0x0 /* Number of Row Access Bits */
+#define MDCNFG_DRAC_13 0x20
+#define MDCNFG_DRAC_14 0x40
+
+#define MDCNFG_DCAC_9 0x0 /* Number of Column Acess Bits */
+#define MDCNFG_DCAC_10 0x08
+#define MDCNFG_DCAC_11 0x10
+
+#define MDCNFG_DBW_16 0x4 /* SDRAM Data Bus width 16bit */
+#define MDCNFG_DCSE1 0x2 /* SDRAM CS 1 Enable */
+#define MDCNFG_DCSE0 0x1 /* SDRAM CS 0 Enable */
+
+
+
/* Data Flash Controller Registers */