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| author | Tom Rix <Tom.Rix@windriver.com> | 2009-09-10 15:27:57 -0400 |
|---|---|---|
| committer | Tom Rix <Tom.Rix@windriver.com> | 2009-10-13 06:17:33 -0500 |
| commit | 7a2aa8b68120f333ed2edc33475ca195810d6cb1 (patch) | |
| tree | 90d5ca33c5e1464bda6f439e4b1f04d164b78d16 /include/asm-arm/arch-omap3/omap3.h | |
| parent | a16df2c11188297eca43cf6080c70fb69b960232 (diff) | |
| download | u-boot-imx-7a2aa8b68120f333ed2edc33475ca195810d6cb1.zip u-boot-imx-7a2aa8b68120f333ed2edc33475ca195810d6cb1.tar.gz u-boot-imx-7a2aa8b68120f333ed2edc33475ca195810d6cb1.tar.bz2 | |
OMAP3 Move cache routine to cache.S
v7_flush_dcache_all, because it depends on omap ROM code is not
generic. Rename the function to 'invalidate_dcache' and move it
to the omap cpu directory.
Collect the other omap cache routines l2_cache_enable and
l2_cache_disable with invalide_dcache into cache.S. This
means removing the old cache.c file that contained l2_cache_enable
and l2_cache_disable.
The conversion from cache.c to cache.S was done most through
disassembling the uboot binary. The only significant change was
to change the comparision for the return of get_cpu_rev from
cmp r0, #0
beq earlier_than_label
Which was lost information to
cmp r0, #CPU_3XX_ES20
blt earlier_than_label
The paths through the enable routine were verified by
adding an infinite loop and seeing the hang. Then
removing the infinite loop and seeing it continue.
The disable routine is similar enough that it was not
tested with this method.
Run tested by cold booting from nand on beagle and zoom1.
Compile tested on MAKEALL arm.
Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
Diffstat (limited to 'include/asm-arm/arch-omap3/omap3.h')
| -rw-r--r-- | include/asm-arm/arch-omap3/omap3.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/include/asm-arm/arch-omap3/omap3.h b/include/asm-arm/arch-omap3/omap3.h index 6459d99..12815f6 100644 --- a/include/asm-arm/arch-omap3/omap3.h +++ b/include/asm-arm/arch-omap3/omap3.h @@ -168,6 +168,8 @@ struct gpio { * ES1 = rev 0 * * ES2 onwards, the value maps to contents of IDCODE register [31:28]. + * + * Note : CPU_3XX_ES20 is used in cache.S. Please review before changing. */ #define CPU_3XX_ES10 0 #define CPU_3XX_ES20 1 |