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| author | Wolfgang Denk <wd@denx.de> | 2008-05-20 16:00:29 +0200 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2008-05-21 00:14:08 +0200 |
| commit | 53677ef18e25c97ac613349087c5cb33ae5a2741 (patch) | |
| tree | f947d34d6efaee2401ea0e4c6104ef2f6a0f7ad0 /include/asm-arm/arch-omap24xx/clocks.h | |
| parent | 727f63334676e760877d43bfb8f0e9331ac8b101 (diff) | |
| download | u-boot-imx-53677ef18e25c97ac613349087c5cb33ae5a2741.zip u-boot-imx-53677ef18e25c97ac613349087c5cb33ae5a2741.tar.gz u-boot-imx-53677ef18e25c97ac613349087c5cb33ae5a2741.tar.bz2 | |
Big white-space cleanup.
This commit gets rid of a huge amount of silly white-space issues.
Especially, all sequences of SPACEs followed by TAB characters get
removed (unless they appear in print statements).
Also remove all embedded "vim:" and "vi:" statements which hide
indentation problems.
Signed-off-by: Wolfgang Denk <wd@denx.de>
Diffstat (limited to 'include/asm-arm/arch-omap24xx/clocks.h')
| -rw-r--r-- | include/asm-arm/arch-omap24xx/clocks.h | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/include/asm-arm/arch-omap24xx/clocks.h b/include/asm-arm/arch-omap24xx/clocks.h index 2a95af1..2e92569 100644 --- a/include/asm-arm/arch-omap24xx/clocks.h +++ b/include/asm-arm/arch-omap24xx/clocks.h @@ -35,9 +35,9 @@ ; PRCM Scheme II ; ; Enable clocks and DPLL for: -; DPLL=300, DPLLout=600 M=1,N=50 CM_CLKSEL1_PLL[21:8] 12/2*50 -; Core=600 (core domain) DPLLx2 CM_CLKSEL2_PLL[1:0] -; MPUF=300 (mpu domain) 2 CM_CLKSEL_MPU[4:0] +; DPLL=300, DPLLout=600 M=1,N=50 CM_CLKSEL1_PLL[21:8] 12/2*50 +; Core=600 (core domain) DPLLx2 CM_CLKSEL2_PLL[1:0] +; MPUF=300 (mpu domain) 2 CM_CLKSEL_MPU[4:0] ; DSPF=200 (dsp domain) 3 CM_CLKSEL_DSP[4:0] ; DSPI=100 6 CM_CLKSEL_DSP[6:5] ; DSP_S bypass CM_CLKSEL_DSP[7] @@ -64,9 +64,9 @@ ; PRCM Scheme III ; ; Enable clocks and DPLL for: -; DPLL=266, DPLLout=532 M=5+1,N=133 CM_CLKSEL1_PLL[21:8] 12/6*133=266 -; Core=532 (core domain) DPLLx2 CM_CLKSEL2_PLL[1:0] -; MPUF=266 (mpu domain) /2 CM_CLKSEL_MPU[4:0] +; DPLL=266, DPLLout=532 M=5+1,N=133 CM_CLKSEL1_PLL[21:8] 12/6*133=266 +; Core=532 (core domain) DPLLx2 CM_CLKSEL2_PLL[1:0] +; MPUF=266 (mpu domain) /2 CM_CLKSEL_MPU[4:0] ; DSPF=177.3 (dsp domain) /3 CM_CLKSEL_DSP[4:0] ; DSPI=88.67 /6 CM_CLKSEL_DSP[6:5] ; DSP_S ACTIVATED CM_CLKSEL_DSP[7] |