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authorAnish Trivedi <anish@freescale.com>2011-06-22 17:49:45 -0500
committerAnish Trivedi <anish@freescale.com>2011-07-05 14:28:09 -0500
commit82102d3fdeae0dcd79d9b3ab7daa96bebd5ad290 (patch)
treea21029195468b8d1ffcc134d8bb25fb6e724eb90 /include/asm-arm/arch-mx6
parentc2ee955784881a2f3ac4c0cc234ba23d83205cb1 (diff)
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ENGR00139206 MX6 USDHC eMMC 4.4 support
New bit definitions in USDHC. Added is_usdhc variable to fsl_esdhc_cfg to distinguish between ESDHC and USDHC. Enabled DDR mode support in USDHC. Created a config to customize target delay for DDR mode. Modified USDHC pad settings to make DDR mode work for all emmcs at 50 MHz. Signed-off-by: Anish Trivedi <anish@freescale.com>
Diffstat (limited to 'include/asm-arm/arch-mx6')
-rw-r--r--include/asm-arm/arch-mx6/mx6_pins.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/include/asm-arm/arch-mx6/mx6_pins.h b/include/asm-arm/arch-mx6/mx6_pins.h
index 2cc7114..f64473a 100644
--- a/include/asm-arm/arch-mx6/mx6_pins.h
+++ b/include/asm-arm/arch-mx6/mx6_pins.h
@@ -48,8 +48,8 @@ typedef enum iomux_config {
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
#define MX6Q_USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
- PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
- PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+ PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
+ PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
#define MX6Q_ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \