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| author | Zhang Jiejing <jiejing.zhang@freescale.com> | 2011-12-14 19:12:20 +0800 |
|---|---|---|
| committer | Zhang Jiejing <jiejing.zhang@freescale.com> | 2011-12-15 11:23:48 +0800 |
| commit | 6dd956ebdeb0d0b247a511de6302903be02802e3 (patch) | |
| tree | 83bce1c11dad0ed46aa20df53b4288c5abed4342 /include/asm-arm/arch-mx6 | |
| parent | a32bc11e6e78753f7f5355a50098c966ff0f40fd (diff) | |
| download | u-boot-imx-6dd956ebdeb0d0b247a511de6302903be02802e3.zip u-boot-imx-6dd956ebdeb0d0b247a511de6302903be02802e3.tar.gz u-boot-imx-6dd956ebdeb0d0b247a511de6302903be02802e3.tar.bz2 | |
ENGR00170299-1 Android: add support fastboot function
add support for otg in MX6Q uboot to enable fastboot function.
Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
Diffstat (limited to 'include/asm-arm/arch-mx6')
| -rw-r--r-- | include/asm-arm/arch-mx6/iomux-v3.h | 5 | ||||
| -rw-r--r-- | include/asm-arm/arch-mx6/mx6.h | 2 | ||||
| -rw-r--r-- | include/asm-arm/arch-mx6/mx6_pins.h | 2 |
3 files changed, 9 insertions, 0 deletions
diff --git a/include/asm-arm/arch-mx6/iomux-v3.h b/include/asm-arm/arch-mx6/iomux-v3.h index 01aeaeb..750cb61 100644 --- a/include/asm-arm/arch-mx6/iomux-v3.h +++ b/include/asm-arm/arch-mx6/iomux-v3.h @@ -140,6 +140,11 @@ int mxc_iomux_v3_setup_pad(iomux_v3_cfg_t pad); int mxc_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t *pad_list, unsigned count); /* + * Set bits for general purpose registers + */ +void mxc_iomux_set_gpr_register(int group, int start_bit, int num_bits, int value); + +/* * Initialise the iomux controller */ void mxc_iomux_v3_init(void *iomux_v3_base); diff --git a/include/asm-arm/arch-mx6/mx6.h b/include/asm-arm/arch-mx6/mx6.h index e7f06fc..81edff6 100644 --- a/include/asm-arm/arch-mx6/mx6.h +++ b/include/asm-arm/arch-mx6/mx6.h @@ -218,6 +218,8 @@ #define WDOG2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x40000) #define CCM_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x44000) #define ANATOP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x48000) +#define USB_PHY0_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x49000) +#define USB_PHY1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4A000) #define SNVS_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4C000) #define EPIT1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x50000) #define EPIT2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x54000) diff --git a/include/asm-arm/arch-mx6/mx6_pins.h b/include/asm-arm/arch-mx6/mx6_pins.h index 97931b5..50fd6f5 100644 --- a/include/asm-arm/arch-mx6/mx6_pins.h +++ b/include/asm-arm/arch-mx6/mx6_pins.h @@ -2251,6 +2251,8 @@ typedef enum iomux_config { IOMUX_PAD(0x05F4, 0x0224, 1, 0x0000, 0, 0) #define _MX6Q_PAD_GPIO_1__KPP_ROW_5 \ IOMUX_PAD(0x05F4, 0x0224, 2, 0x08F4, 0, 0) +#define MX6Q_PAD_GPIO_1__USBOTG_ID \ + IOMUX_PAD(0x05F4, 0x0224, 3, 0x0000, 0, MX6Q_USDHC_PAD_CTRL) #define _MX6Q_PAD_GPIO_1__PWM2_PWMO \ IOMUX_PAD(0x05F4, 0x0224, 4, 0x0000, 0, 0) #define _MX6Q_PAD_GPIO_1__GPIO_1_1 \ |