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authorSandor Yu <r01008@freescale.com>2011-09-01 17:41:36 +0800
committerSandor Yu <R01008@freescale.com>2011-09-02 17:28:42 +0800
commit799007675f0bd42bae7397056a2cde250b8811ec (patch)
tree6237cf9141803d551624ef135d132ac8ed463a0c /include/asm-arm/arch-mx6/mx6.h
parent7db399587fe4cd8d0e77491e9b2fad47c0a82be2 (diff)
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ENGR00139254: Enable MX6Q Uboot Splash Screen
Only support LVDS0 splash screen. Enable splash process: 1.define CONFIG_SPLASH_SCREEN in mx6q_sabreauto.h 2.Config U-boot with followed command:() setenv splashimage '0x30000000' #Set splash position as Center setenv splashpos 'm,m' #Set LVDS via LVDS bridge 0 setenv lvds_num 0 Signed-off-by: Sandor Yu <r01008@freescale.com>
Diffstat (limited to 'include/asm-arm/arch-mx6/mx6.h')
-rw-r--r--include/asm-arm/arch-mx6/mx6.h7
1 files changed, 6 insertions, 1 deletions
diff --git a/include/asm-arm/arch-mx6/mx6.h b/include/asm-arm/arch-mx6/mx6.h
index 772290a..1a984de 100644
--- a/include/asm-arm/arch-mx6/mx6.h
+++ b/include/asm-arm/arch-mx6/mx6.h
@@ -65,6 +65,11 @@
* @ingroup MSL_MX6
*/
+/*
+ * IPU
+ */
+#define IPU_CTRL_BASE_ADDR 0x02400000
+
/*!
* Register an interrupt handler for the SMN as well as the SCC. In some
* implementations, the SMN is not connected at all, and in others, it is
@@ -575,7 +580,7 @@
#define CLKCTL_CS1CDR 0x28
#define CLKCTL_CS2CDR 0x2C
#define CLKCTL_CDCDR 0x30
-#define CLKCTL_CHSCDR 0x34
+#define CLKCTL_CHSCCDR 0x34
#define CLKCTL_CSCDR2 0x38
#define CLKCTL_CSCDR3 0x3C
#define CLKCTL_CSCDR4 0x40