ENGR00169919 MX6Q ARM2 U-Boot : Support Pop CPU Board

Add support for MX6Q ARM2 LPDDR2 POP CPU Board. Change thing include
- TEXT_BASE
- RAM address and size
- Initialization DCD
- MMU related code

Use mx6q_arm2_lpddr2pop_config as the build config. After u-boot.bin is
generated, set the board to serial download mode, use sb loader to run the
bootloader.

There is one line in the original DDR initialization script
setmem /32 0x00B00000 = 0x1
however this address can not be accessed by DCD. A try to add it later in
"dram_init" block the boot up. Waiting for IC team to give an explanation
on it. Hold temperorily

The MMU Change can be concluded as the following
 - Cacheable and Uncacheable SDRAM allocation changes to
	Phys		Virtual		Size		Property
	----------	----------	--------	----------
	0x10000000	0x10000000	256M		cacheable
	0x80000000	0x20000000	16M		uncacheable
	0x81000000	0x21000000	240M		cacheable

 - TEXT_BASE change to 0x10800000, which reserves 8MB of memory at the start
   of SDRAM. This address makes sure that the text section of U-boot have the
   same Physical and Virtural address, thus the PC don't need to change when
   MMU is enabled. Also the text section is all allocated in cacheable memory,
   which may increase excecution performance.

 - Since this SDRAM allocation avoid overlap in physical memory between
   cacheable and uncacheable memory, the implementation of __ioremap can be
   ignored

Signed-off-by: Eric Sun <jian.sun@freescale.com>

1 files changed, 17 insertions, 0 deletions

diff --git a/include/asm-arm/arch-mx6/mmu.h b/include/asm-arm/arch-mx6/mmu.h
index d571f59..ee78ffb 100644
--- a/include/asm-arm/arch-mx6/mmu.h
+++ b/include/asm-arm/arch-mx6/mmu.h
@@ -140,10 +140,18 @@ union ARM_MMU_FIRST_LEVEL_DESCRIPTOR {
  */
 inline unsigned long iomem_to_phys(unsigned long virt)
 {
+#ifndef CONFIG_MX6Q_ARM2_LPDDR2POP
 	if (virt >= 0x88000000 && virt <= 0xffffffff)
 		return (unsigned long)(virt - 0x78000000);
 
 	return (unsigned long)virt;
+#else
+	/* bank 2 : virt 0x20000000 ~ phy 0x80000000, size 256MB */
+	if (virt >= 0x20000000 && virt <= 0x30000000)
+		return (unsigned long)(virt + 0x60000000);
+
+	return (unsigned long)virt;
+#endif
 }
 
 /*
@@ -152,6 +160,7 @@ inline unsigned long iomem_to_phys(unsigned long virt)
  */
 void *__ioremap(unsigned long offset, size_t size, unsigned long flags)
 {
+#ifndef CONFIG_MX6Q_ARM2_LPDDR2POP
 	if (1 == flags) {
 		if (offset >= PHYS_SDRAM_1 &&
 		offset < (unsigned long)(PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE))
@@ -160,6 +169,14 @@ void *__ioremap(unsigned long offset, size_t size, unsigned long flags)
 			return NULL;
 	} else
 		return (void *)offset;
+#else
+	/*
+	 * In case the cacheable and uncacheable memory don't overlap in
+	 * physical memory, this function is no longer needed, we simply return
+	 * the first address itself
+	 */
+	return (void *)offset;
+#endif
 }
 
 /*