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| author | Terry Lv <r65388@freescale.com> | 2010-08-02 19:54:41 +0800 |
|---|---|---|
| committer | Terry Lv <r65388@freescale.com> | 2010-08-03 16:35:23 +0800 |
| commit | 70d1be1c21e1ee63df7593eb0bd733dfaae6a2da (patch) | |
| tree | d22787d6fc53c94f06cc8f10886ccb7f69ab3a6e /include/asm-arm/arch-mx50 | |
| parent | 9da7bd8c3a3bc34d6a3014edb86827964ff94dcb (diff) | |
| download | u-boot-imx-70d1be1c21e1ee63df7593eb0bd733dfaae6a2da.zip u-boot-imx-70d1be1c21e1ee63df7593eb0bd733dfaae6a2da.tar.gz u-boot-imx-70d1be1c21e1ee63df7593eb0bd733dfaae6a2da.tar.bz2 | |
ENGR00125324: Add splash screen code and support for epdcrel-imx-2.6.31-10.08.01rel-imx-2.6.31-10.08.00
Add splash screen code and support for epdc.
Signed-off-by: Terry Lv <r65388@freescale.com>
Diffstat (limited to 'include/asm-arm/arch-mx50')
| -rw-r--r-- | include/asm-arm/arch-mx50/mx50.h | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/include/asm-arm/arch-mx50/mx50.h b/include/asm-arm/arch-mx50/mx50.h index d5e0d2c..2395252 100644 --- a/include/asm-arm/arch-mx50/mx50.h +++ b/include/asm-arm/arch-mx50/mx50.h @@ -43,6 +43,7 @@ #define CTI3_BASE_ADDR (DEBUG_BASE_ADDR + 0x00007000) #define CORTEX_DBG_BASE_ADDR (DEBUG_BASE_ADDR + 0x00008000) #define OCOTP_CTRL_BASE_ADDR (DEBUG_BASE_ADDR + 0x01002000) +#define EPDC_BASE_ADDR (DEBUG_BASE_ADDR + 0x01010000) /* * SPBA global module enabled #0 @@ -135,6 +136,35 @@ #define FEC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000EC000) /* + * Some of i.MX50 SoC registers are associated with four addresses + * used for different operations - read/write, set, clear and toggle bits. + * + * Some of registers do not implement such feature and, thus, should be + * accessed/manipulated via single address in common way. + */ +#define REG_RD(base, reg) \ + (*(volatile unsigned int *)((base) + (reg))) +#define REG_WR(base, reg, value) \ + ((*(volatile unsigned int *)((base) + (reg))) = (value)) +#define REG_SET(base, reg, value) \ + ((*(volatile unsigned int *)((base) + (reg ## _SET))) = (value)) +#define REG_CLR(base, reg, value) \ + ((*(volatile unsigned int *)((base) + (reg ## _CLR))) = (value)) +#define REG_TOG(base, reg, value) \ + ((*(volatile unsigned int *)((base) + (reg ## _TOG))) = (value)) + +#define REG_RD_ADDR(addr) \ + (*(volatile unsigned int *)((addr))) +#define REG_WR_ADDR(addr, value) \ + ((*(volatile unsigned int *)((addr))) = (value)) +#define REG_SET_ADDR(addr, value) \ + ((*(volatile unsigned int *)((addr) + 0x4)) = (value)) +#define REG_CLR_ADDR(addr, value) \ + ((*(volatile unsigned int *)((addr) + 0x8)) = (value)) +#define REG_TOG_ADDR(addr, value) \ + ((*(volatile unsigned int *)((addr) + 0xc)) = (value)) + +/* * Memory regions and CS */ #define CSD0_BASE_ADDR 0x70000000 |