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authorTerry Lv <r65388@freescale.com>2010-09-05 18:27:46 +0800
committerTerry Lv <r65388@freescale.com>2010-09-19 23:25:21 +0800
commit6537dffd192344d8c786a037bce9f41db5448fc9 (patch)
tree0500e0c88f7b0c9c6675d14fad3563267b419936 /include/asm-arm/arch-mx50
parent1e981afa607f3e04691fa8f05dc7c37070702845 (diff)
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ENGR00127167: Add gpmi nfc and apbh dma support for mx50.
Add gpmi nfc and apbh dma support for mx50. Signed-off-by: Terry Lv <r65388@freescale.com>
Diffstat (limited to 'include/asm-arm/arch-mx50')
-rw-r--r--include/asm-arm/arch-mx50/mmu.h37
-rw-r--r--include/asm-arm/arch-mx50/mx50.h5
-rw-r--r--include/asm-arm/arch-mx50/mx50_pins.h1
3 files changed, 6 insertions, 37 deletions
diff --git a/include/asm-arm/arch-mx50/mmu.h b/include/asm-arm/arch-mx50/mmu.h
index 29e8091..502b94c 100644
--- a/include/asm-arm/arch-mx50/mmu.h
+++ b/include/asm-arm/arch-mx50/mmu.h
@@ -143,41 +143,4 @@ union ARM_MMU_FIRST_LEVEL_DESCRIPTOR {
ARM_ACCESS_TYPE_NO_ACCESS(14) | \
ARM_ACCESS_TYPE_NO_ACCESS(15))
-/*
- * Translate the virtual address of ram space to physical address
- * It is dependent on the implementation of mmu_init
- */
-inline void *iomem_to_phys(unsigned long virt)
-{
- if (virt >= 0xB0000000)
- return (void *)((virt - 0xB0000000) + PHYS_SDRAM_1);
-
- return (void *)virt;
-}
-
-/*
- * remap the physical address of ram space to uncacheable virtual address space
- * It is dependent on the implementation of hal_mmu_init
- */
-void *__ioremap(unsigned long offset, size_t size, unsigned long flags)
-{
- if (1 == flags) {
- if (offset >= PHYS_SDRAM_1 &&
- offset < (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE))
- return (void *)(offset - PHYS_SDRAM_1) + 0xB0000000;
- else
- return NULL;
- } else
- return (void *)offset;
-}
-
-/*
- * Remap the physical address of ram space to uncacheable virtual address space
- * It is dependent on the implementation of hal_mmu_init
- */
-void __iounmap(void *addr)
-{
- return;
-}
-
#endif
diff --git a/include/asm-arm/arch-mx50/mx50.h b/include/asm-arm/arch-mx50/mx50.h
index 2395252..69e639c 100644
--- a/include/asm-arm/arch-mx50/mx50.h
+++ b/include/asm-arm/arch-mx50/mx50.h
@@ -42,7 +42,10 @@
#define CTI2_BASE_ADDR (DEBUG_BASE_ADDR + 0x00006000)
#define CTI3_BASE_ADDR (DEBUG_BASE_ADDR + 0x00007000)
#define CORTEX_DBG_BASE_ADDR (DEBUG_BASE_ADDR + 0x00008000)
+#define ABPHDMA_BASE_ADDR (DEBUG_BASE_ADDR + 0x01000000)
#define OCOTP_CTRL_BASE_ADDR (DEBUG_BASE_ADDR + 0x01002000)
+#define GPMI_BASE_ADDR (DEBUG_BASE_ADDR + 0x01006000)
+#define BCH_BASE_ADDR (DEBUG_BASE_ADDR + 0x01008000)
#define EPDC_BASE_ADDR (DEBUG_BASE_ADDR + 0x01010000)
/*
@@ -306,6 +309,8 @@ enum mxc_clock {
MXC_ESDHC2_CLK,
MXC_ESDHC3_CLK,
MXC_ESDHC4_CLK,
+ MXC_GPMI_CLK,
+ MXC_BCH_CLK,
};
enum mxc_peri_clocks {
diff --git a/include/asm-arm/arch-mx50/mx50_pins.h b/include/asm-arm/arch-mx50/mx50_pins.h
index 05935c9..311d434 100644
--- a/include/asm-arm/arch-mx50/mx50_pins.h
+++ b/include/asm-arm/arch-mx50/mx50_pins.h
@@ -69,6 +69,7 @@
#define NON_PAD_I PIN_TO_PAD_MASK
#define MUX_I_START 0x0020
#define PAD_I_START 0x2CC
+#define PAD_GRP_START 0x668
#define INPUT_CTL_START 0x6C4
#define MUX_I_END (PAD_I_START - 4)