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| author | Anish Trivedi <anish@freescale.com> | 2011-05-05 13:16:17 -0500 |
|---|---|---|
| committer | Anish Trivedi <anish@freescale.com> | 2011-05-10 11:38:23 -0500 |
| commit | c53f846a0b72a22f65f07b9eb6638168cc7004a9 (patch) | |
| tree | 771deedcdd90af9bb725b474ddc10219f86cf061 /include/asm-arm/arch-mx50/mx50.h | |
| parent | 6fc284a6a40dff807f1598e1c3ebda6cfb28cc8f (diff) | |
| download | u-boot-imx-c53f846a0b72a22f65f07b9eb6638168cc7004a9.zip u-boot-imx-c53f846a0b72a22f65f07b9eb6638168cc7004a9.tar.gz u-boot-imx-c53f846a0b72a22f65f07b9eb6638168cc7004a9.tar.bz2 | |
ENGR00142995 MX50: Enable uSDHC instead of eSDHC for SDR mode
On SD3 on MX50, there is an option to choose eSDHC or uSDHC controller.
By default eSDHC is selected. However, eSDHC shows some borderline timing
in SDR mode at 50 MHz, whereas uSDHC shows borderline timing in DDR mode
at 50 MHz. Therefore, add a compile time option to uboot for MX50 to
select uSDHC in SDR mode or eSDHC in DDR mode on SD3 port.
By default the compile time option, CONFIG_MX50_ENABLE_USDHC_SDR,
is commented out in the include/configs/mx50_<board>.h file to
select eSDHC with DDR mode enabled. Uncomment the define to select
uSDHC with only SDR mode enabled.
Also increased max frequency supported by ESDHC to 52 MHz instead
of 50 MHz.
Signed-off-by: Anish Trivedi <anish@freescale.com>
Diffstat (limited to 'include/asm-arm/arch-mx50/mx50.h')
| -rw-r--r-- | include/asm-arm/arch-mx50/mx50.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/asm-arm/arch-mx50/mx50.h b/include/asm-arm/arch-mx50/mx50.h index 9c905e5..c004951 100644 --- a/include/asm-arm/arch-mx50/mx50.h +++ b/include/asm-arm/arch-mx50/mx50.h @@ -44,6 +44,7 @@ #define CORTEX_DBG_BASE_ADDR (DEBUG_BASE_ADDR + 0x00008000) #define ABPHDMA_BASE_ADDR (DEBUG_BASE_ADDR + 0x01000000) #define OCOTP_CTRL_BASE_ADDR (DEBUG_BASE_ADDR + 0x01002000) +#define DIGCTL_BASE_ADDR (DEBUG_BASE_ADDR + 0x01004000) #define GPMI_BASE_ADDR (DEBUG_BASE_ADDR + 0x01006000) #define BCH_BASE_ADDR (DEBUG_BASE_ADDR + 0x01008000) #define EPDC_BASE_ADDR (DEBUG_BASE_ADDR + 0x01010000) |