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authorWolfgang Denk <wd@castor.denx.de>2006-05-30 15:56:48 +0200
committerWolfgang Denk <wd@castor.denx.de>2006-05-30 15:56:48 +0200
commitba94a1bba3600d387edba7eb451990d9891e1c2f (patch)
treee84f737ac88e15342b4cab23c9e631987e8ee75e /include/asm-arm/arch-ixp/ixp425.h
parent5770a1e488621a9e7e344afed7c921ff4e715a63 (diff)
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* Update Intel IXP4xx support
- Add IXP4xx NPE ethernet MAC support - Add support for Intel IXDPG425 board - Add support for Prodrive PDNB3 board - Add IRQ support Patch by Stefan Roese, 23 May 2006 [This patch does not include cpu/ixp/npe/IxNpeMicrocode.c which still sufferes from licensing issues. Blame Intel.]
Diffstat (limited to 'include/asm-arm/arch-ixp/ixp425.h')
-rw-r--r--include/asm-arm/arch-ixp/ixp425.h56
1 files changed, 20 insertions, 36 deletions
diff --git a/include/asm-arm/arch-ixp/ixp425.h b/include/asm-arm/arch-ixp/ixp425.h
index fbe6858..11dc356 100644
--- a/include/asm-arm/arch-ixp/ixp425.h
+++ b/include/asm-arm/arch-ixp/ixp425.h
@@ -73,21 +73,18 @@
* PCI Configuration space
*/
#define IXP425_PCI_CFG_BASE_PHYS (0xC0000000)
-#define IXP425_PCI_CFG_BASE_VIRT (0xFFFD0000)
#define IXP425_PCI_CFG_REGION_SIZE (0x00001000)
/*
* Expansion BUS Configuration registers
*/
#define IXP425_EXP_CFG_BASE_PHYS (0xC4000000)
-#define IXP425_EXP_CFG_BASE_VIRT (0xFFFD1000)
#define IXP425_EXP_CFG_REGION_SIZE (0x00001000)
/*
* Peripheral space
*/
#define IXP425_PERIPHERAL_BASE_PHYS (0xC8000000)
-#define IXP425_PERIPHERAL_BASE_VIRT (0xFFFD2000)
#define IXP425_PERIPHERAL_REGION_SIZE (0x0000C000)
/*
@@ -99,7 +96,6 @@
* Q Manager space .. not static mapped
*/
#define IXP425_QMGR_BASE_PHYS (0x60000000)
-#define IXP425_QMGR_BASE_VIRT (0xFFFDE000)
#define IXP425_QMGR_REGION_SIZE (0x00004000)
/*
@@ -113,10 +109,8 @@
*/
#define IXP425_EXP_BUS_BASE1_PHYS (0x00000000)
#define IXP425_EXP_BUS_BASE2_PHYS (0x50000000)
-#define IXP425_EXP_BUS_BASE2_VIRT (0xF0000000)
#define IXP425_EXP_BUS_BASE_PHYS IXP425_EXP_BUS_BASE2_PHYS
-#define IXP425_EXP_BUS_BASE_VIRT IXP425_EXP_BUS_BASE2_VIRT
#define IXP425_EXP_BUS_REGION_SIZE (0x08000000)
#define IXP425_EXP_BUS_CSX_REGION_SIZE (0x01000000)
@@ -130,20 +124,10 @@
#define IXP425_EXP_BUS_CS6_BASE_PHYS (IXP425_EXP_BUS_BASE2_PHYS + 0x06000000)
#define IXP425_EXP_BUS_CS7_BASE_PHYS (IXP425_EXP_BUS_BASE2_PHYS + 0x07000000)
-#define IXP425_EXP_BUS_CS0_BASE_VIRT (IXP425_EXP_BUS_BASE2_VIRT + 0x00000000)
-#define IXP425_EXP_BUS_CS1_BASE_VIRT (IXP425_EXP_BUS_BASE2_VIRT + 0x01000000)
-#define IXP425_EXP_BUS_CS2_BASE_VIRT (IXP425_EXP_BUS_BASE2_VIRT + 0x02000000)
-#define IXP425_EXP_BUS_CS3_BASE_VIRT (IXP425_EXP_BUS_BASE2_VIRT + 0x03000000)
-#define IXP425_EXP_BUS_CS4_BASE_VIRT (IXP425_EXP_BUS_BASE2_VIRT + 0x04000000)
-#define IXP425_EXP_BUS_CS5_BASE_VIRT (IXP425_EXP_BUS_BASE2_VIRT + 0x05000000)
-#define IXP425_EXP_BUS_CS6_BASE_VIRT (IXP425_EXP_BUS_BASE2_VIRT + 0x06000000)
-#define IXP425_EXP_BUS_CS7_BASE_VIRT (IXP425_EXP_BUS_BASE2_VIRT + 0x07000000)
-
#define IXP425_FLASH_WRITABLE (0x2)
#define IXP425_FLASH_DEFAULT (0xbcd23c40)
#define IXP425_FLASH_WRITE (0xbcd23c42)
-
#define IXP425_EXP_CS0_OFFSET 0x00
#define IXP425_EXP_CS1_OFFSET 0x04
#define IXP425_EXP_CS2_OFFSET 0x08
@@ -161,7 +145,7 @@
* Expansion Bus Controller registers.
*/
#ifndef __ASSEMBLY__
-#define IXP425_EXP_REG(x) ((volatile u32 *)(IXP425_EXP_CFG_BASE_VIRT+(x)))
+#define IXP425_EXP_REG(x) ((volatile u32 *)(IXP425_EXP_CFG_BASE_PHYS+(x)))
#else
#define IXP425_EXP_REG(x) (IXP425_EXP_CFG_BASE_PHYS+(x))
#endif
@@ -288,7 +272,6 @@
#define MSR_DDSR (1 << 1) /* Delta Data Set Ready */
#define MSR_DCTS (1 << 0) /* Delta Clear To Send */
-#define IXP425_CONSOLE_UART_BASE_VIRT IXP425_UART1_BASE_VIRT
#define IXP425_CONSOLE_UART_BASE_PHYS IXP425_UART1_BASE_PHYS
/*
* Peripheral Space Registers
@@ -306,20 +289,6 @@
#define IXP425_EthB_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0xA000)
#define IXP425_USB_BASE_PHYS (IXP425_PERIPHERAL_BASE_PHYS + 0xB000)
-#define IXP425_UART1_BASE_VIRT (IXP425_PERIPHERAL_BASE_VIRT + 0x0000)
-#define IXP425_UART2_BASE_VIRT (IXP425_PERIPHERAL_BASE_VIRT + 0x1000)
-#define IXP425_PMU_BASE_VIRT (IXP425_PERIPHERAL_BASE_VIRT + 0x2000)
-#define IXP425_INTC_BASE_VIRT (IXP425_PERIPHERAL_BASE_VIRT + 0x3000)
-#define IXP425_GPIO_BASE_VIRT (IXP425_PERIPHERAL_BASE_VIRT + 0x4000)
-#define IXP425_TIMER_BASE_VIRT (IXP425_PERIPHERAL_BASE_VIRT + 0x5000)
-#define IXP425_NPEA_BASE_VIRT (IXP425_PERIPHERAL_BASE_VIRT + 0x6000)
-#define IXP425_NPEB_BASE_VIRT (IXP425_PERIPHERAL_BASE_VIRT + 0x7000)
-#define IXP425_NPEC_BASE_VIRT (IXP425_PERIPHERAL_BASE_VIRT + 0x8000)
-#define IXP425_EthA_BASE_VIRT (IXP425_PERIPHERAL_BASE_VIRT + 0x9000)
-#define IXP425_EthB_BASE_VIRT (IXP425_PERIPHERAL_BASE_VIRT + 0xA000)
-#define IXP425_USB_BASE_VIRT (IXP425_PERIPHERAL_BASE_VIRT + 0xB000)
-
-
/*
* UART Register Definitions , Offsets only as there are 2 UARTS.
* IXP425_UART1_BASE , IXP425_UART2_BASE.
@@ -341,11 +310,14 @@
#define IXP425_ICIH_OFFSET 0x18 /* IRQ Highest Pri Int */
#define IXP425_ICFH_OFFSET 0x1C /* FIQ Highest Pri Int */
+#define N_IRQS 32
+#define IXP425_TIMER_2_IRQ 11
+
/*
* Interrupt Controller Register Definitions.
*/
#ifndef __ASSEMBLY__
-#define IXP425_INTC_REG(x) ((volatile u32 *)(IXP425_INTC_BASE_VIRT+(x)))
+#define IXP425_INTC_REG(x) ((volatile u32 *)(IXP425_INTC_BASE_PHYS+(x)))
#else
#define IXP425_INTC_REG(x) (IXP425_INTC_BASE_PHYS+(x))
#endif
@@ -375,7 +347,7 @@
* GPIO Register Definitions.
* [Only perform 32bit reads/writes]
*/
-#define IXP425_GPIO_REG(x) ((volatile u32 *)(IXP425_GPIO_BASE_VIRT+(x)))
+#define IXP425_GPIO_REG(x) ((volatile u32 *)(IXP425_GPIO_BASE_PHYS+(x)))
#define IXP425_GPIO_GPOUTR IXP425_GPIO_REG(IXP425_GPIO_GPOUTR_OFFSET)
#define IXP425_GPIO_GPOER IXP425_GPIO_REG(IXP425_GPIO_GPOER_OFFSET)
@@ -387,6 +359,16 @@
#define IXP425_GPIO_GPDBSELR IXP425_GPIO_REG(IXP425_GPIO_GPDBSELR_OFFSET)
/*
+ * Macros to make it easy to access the GPIO registers
+ */
+#define GPIO_OUTPUT_ENABLE(line) *IXP425_GPIO_GPOER &= ~(1 << (line))
+#define GPIO_OUTPUT_DISABLE(line) *IXP425_GPIO_GPOER |= (1 << (line))
+#define GPIO_OUTPUT_SET(line) *IXP425_GPIO_GPOUTR |= (1 << (line))
+#define GPIO_OUTPUT_CLEAR(line) *IXP425_GPIO_GPOUTR &= ~(1 << (line))
+#define GPIO_INT_ACT_LOW_SET(line) *IXP425_GPIO_GPIT1R = \
+ (*IXP425_GPIO_GPIT1R & ~(0x7 << (line * 3))) | (0x1 << (line * 3))
+
+/*
* Constants to make it easy to access Timer Control/Status registers
*/
#define IXP425_OSTS_OFFSET 0x00 /* Continious TimeStamp */
@@ -409,7 +391,9 @@
#define IXP425_TIMER_REG(x) (IXP425_TIMER_BASE_PHYS+(x))
#endif
+#if 0 /* test-only: also defined in npe/include/... */
#define IXP425_OSTS IXP425_TIMER_REG(IXP425_OSTS_OFFSET)
+#endif
#define IXP425_OST1 IXP425_TIMER_REG(IXP425_OST1_OFFSET)
#define IXP425_OSRT1 IXP425_TIMER_REG(IXP425_OSRT1_OFFSET)
#define IXP425_OST2 IXP425_TIMER_REG(IXP425_OST2_OFFSET)
@@ -457,12 +441,12 @@
#define PCI_ATPDMA0_LENADDR_OFFSET 0x48
#define PCI_ATPDMA1_AHBADDR_OFFSET 0x4C
#define PCI_ATPDMA1_PCIADDR_OFFSET 0x50
-#define PCI_ATPDMA1_LENADDR_OFFSET 0x54
+#define PCI_ATPDMA1_LENADDR_OFFSET 0x54
/*
* PCI Control/Status Registers
*/
-#define IXP425_PCI_CSR(x) ((volatile u32 *)(IXP425_PCI_CFG_BASE_VIRT+(x)))
+#define IXP425_PCI_CSR(x) ((volatile u32 *)(IXP425_PCI_CFG_BASE_PHYS+(x)))
#define PCI_NP_AD IXP425_PCI_CSR(PCI_NP_AD_OFFSET)
#define PCI_NP_CBE IXP425_PCI_CSR(PCI_NP_CBE_OFFSET)