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authorSandeep Paulraj <s-paulraj@ti.com>2009-08-18 10:10:42 -0400
committerScott Wood <scottwood@freescale.com>2009-08-26 15:37:03 -0500
commit77b351cd0f20483eefa09bebebb3e0cbf5555b2c (patch)
treee28967858ff93cc952c91a52e3095d96c6eb27b9 /include/asm-arm/arch-davinci
parentf83b7f9e8a5d1334e24506ea5953dd871596ea8a (diff)
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NAND: DaVinci: V2 Adding 4 BIT ECC support
This patch adds 4 BIT ECC support in the DaVinci NAND driver. Tested on both the DM355 and DM365. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
Diffstat (limited to 'include/asm-arm/arch-davinci')
-rw-r--r--include/asm-arm/arch-davinci/emif_defs.h10
1 files changed, 10 insertions, 0 deletions
diff --git a/include/asm-arm/arch-davinci/emif_defs.h b/include/asm-arm/arch-davinci/emif_defs.h
index 646fc77..c91e30c 100644
--- a/include/asm-arm/arch-davinci/emif_defs.h
+++ b/include/asm-arm/arch-davinci/emif_defs.h
@@ -55,6 +55,16 @@ typedef struct {
dv_reg NANDF2ECC;
dv_reg NANDF3ECC;
dv_reg NANDF4ECC;
+ u_int8_t RSVD2[60];
+ dv_reg NAND4BITECCLOAD;
+ dv_reg NAND4BITECC1;
+ dv_reg NAND4BITECC2;
+ dv_reg NAND4BITECC3;
+ dv_reg NAND4BITECC4;
+ dv_reg NANDERRADD1;
+ dv_reg NANDERRADD2;
+ dv_reg NANDERRVAL1;
+ dv_reg NANDERRVAL2;
} emif_registers;
typedef emif_registers *emifregs;