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author | Stefan Roese <sr@denx.de> | 2007-08-15 14:51:27 +0200 |
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committer | Stefan Roese <sr@denx.de> | 2007-08-15 14:51:27 +0200 |
commit | d61ea14885631e58a25feaa81ee82eb464c62d6a (patch) | |
tree | 27927975039d0a15e6c6d4dfe8f765a76a12820a /include/asm-arm/arch-davinci/emif_defs.h | |
parent | 3ba4c2d68f6541db4677b4aea12071f56e6ff6e6 (diff) | |
parent | 594e79838ce5078a90d0c27abb2b2d61d5f8e8a7 (diff) | |
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Merge with git://www.denx.de/git/u-boot.git
Diffstat (limited to 'include/asm-arm/arch-davinci/emif_defs.h')
-rw-r--r-- | include/asm-arm/arch-davinci/emif_defs.h | 61 |
1 files changed, 61 insertions, 0 deletions
diff --git a/include/asm-arm/arch-davinci/emif_defs.h b/include/asm-arm/arch-davinci/emif_defs.h new file mode 100644 index 0000000..646fc77 --- /dev/null +++ b/include/asm-arm/arch-davinci/emif_defs.h @@ -0,0 +1,61 @@ +/* + * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _EMIF_DEFS_H_ +#define _EMIF_DEFS_H_ + +#include <asm/arch/hardware.h> + +typedef struct { + dv_reg ERCSR; + dv_reg AWCCR; + dv_reg SDBCR; + dv_reg SDRCR; + dv_reg AB1CR; + dv_reg AB2CR; + dv_reg AB3CR; + dv_reg AB4CR; + dv_reg SDTIMR; + dv_reg DDRSR; + dv_reg DDRPHYCR; + dv_reg DDRPHYSR; + dv_reg TOTAR; + dv_reg TOTACTR; + dv_reg DDRPHYID_REV; + dv_reg SDSRETR; + dv_reg EIRR; + dv_reg EIMR; + dv_reg EIMSR; + dv_reg EIMCR; + dv_reg IOCTRLR; + dv_reg IOSTATR; + u_int8_t RSVD0[8]; + dv_reg NANDFCR; + dv_reg NANDFSR; + u_int8_t RSVD1[8]; + dv_reg NANDF1ECC; + dv_reg NANDF2ECC; + dv_reg NANDF3ECC; + dv_reg NANDF4ECC; +} emif_registers; + +typedef emif_registers *emifregs; +#endif |