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authorMarkus Klotzbuecher <mk@denx.de>2008-07-10 10:26:07 +0200
committerMarkus Klotzbuecher <mk@denx.de>2008-07-10 10:26:07 +0200
commit794a5924972fc8073616e98a2668da4a5f9aea90 (patch)
treedd0db39b3e183b5bcb0300d5377d7a0d5ac5fd0c /include/asm-arm/arch-at91sam9/at91cap9.h
parentf2aeecc320f5b181b30effcaa67683aec8d5a843 (diff)
parent4188f0491886b3b486164e819c0a83fdb97efd7d (diff)
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Merge branch 'master' of git://www.denx.de/git/u-boot
Diffstat (limited to 'include/asm-arm/arch-at91sam9/at91cap9.h')
-rw-r--r--include/asm-arm/arch-at91sam9/at91cap9.h14
1 files changed, 13 insertions, 1 deletions
diff --git a/include/asm-arm/arch-at91sam9/at91cap9.h b/include/asm-arm/arch-at91sam9/at91cap9.h
index d1b33a0..0b52228 100644
--- a/include/asm-arm/arch-at91sam9/at91cap9.h
+++ b/include/asm-arm/arch-at91sam9/at91cap9.h
@@ -101,13 +101,25 @@
#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS)
#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS)
#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
-#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS)
+#define AT91_SCKCR (0xfffffd50 - AT91_BASE_SYS)
+#define AT91_GPBR_REVB (0xfffffd50 - AT91_BASE_SYS)
+#define AT91_GPBR_REVC (0xfffffd60 - AT91_BASE_SYS)
#define AT91_USART0 AT91CAP9_BASE_US0
#define AT91_USART1 AT91CAP9_BASE_US1
#define AT91_USART2 AT91CAP9_BASE_US2
/*
+ * SCKCR flags
+ */
+#define AT91CAP9_SCKCR_RCEN (1 << 0) /* RC Oscillator Enable */
+#define AT91CAP9_SCKCR_OSC32EN (1 << 1) /* 32kHz Oscillator Enable */
+#define AT91CAP9_SCKCR_OSC32BYP (1 << 2) /* 32kHz Oscillator Bypass */
+#define AT91CAP9_SCKCR_OSCSEL (1 << 3) /* Slow Clock Selector */
+#define AT91CAP9_SCKCR_OSCSEL_RC (0 << 3)
+#define AT91CAP9_SCKCR_OSCSEL_32 (1 << 3)
+
+/*
* Internal Memory.
*/
#define AT91CAP9_SRAM_BASE 0x00100000 /* Internal SRAM base address */