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| author | Stelian Pop <stelian@popies.net> | 2008-05-08 14:52:34 +0200 |
|---|---|---|
| committer | Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | 2008-05-10 11:45:03 +0200 |
| commit | 19883aede2ac0a522493bfb2b35a7dbb200071b1 (patch) | |
| tree | 0cfee61893ab65993b6e56ad4f2590de7031a9d9 /include/asm-arm/arch-at91sam9/at91cap9.h | |
| parent | 098b7b4b441b12c2a64dd517930f43c793542759 (diff) | |
| download | u-boot-imx-19883aede2ac0a522493bfb2b35a7dbb200071b1.zip u-boot-imx-19883aede2ac0a522493bfb2b35a7dbb200071b1.tar.gz u-boot-imx-19883aede2ac0a522493bfb2b35a7dbb200071b1.tar.bz2 | |
Support AT91CAP9 revC CPUs
The AT91CAP9 revC CPU has a few differences over the previous,
revB CPU which was distributed in small quantities only (revA was
an internal Atmel product only).
The revC silicon needs a special initialisation sequence to
switch from the internal (imprecise) RC oscillator to the
external 32k clock.
Signed-off-by: Stelian Pop <stelian@popies.net>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Diffstat (limited to 'include/asm-arm/arch-at91sam9/at91cap9.h')
| -rw-r--r-- | include/asm-arm/arch-at91sam9/at91cap9.h | 14 |
1 files changed, 13 insertions, 1 deletions
diff --git a/include/asm-arm/arch-at91sam9/at91cap9.h b/include/asm-arm/arch-at91sam9/at91cap9.h index d1b33a0..0b52228 100644 --- a/include/asm-arm/arch-at91sam9/at91cap9.h +++ b/include/asm-arm/arch-at91sam9/at91cap9.h @@ -101,13 +101,25 @@ #define AT91_RTT (0xfffffd20 - AT91_BASE_SYS) #define AT91_PIT (0xfffffd30 - AT91_BASE_SYS) #define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) -#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS) +#define AT91_SCKCR (0xfffffd50 - AT91_BASE_SYS) +#define AT91_GPBR_REVB (0xfffffd50 - AT91_BASE_SYS) +#define AT91_GPBR_REVC (0xfffffd60 - AT91_BASE_SYS) #define AT91_USART0 AT91CAP9_BASE_US0 #define AT91_USART1 AT91CAP9_BASE_US1 #define AT91_USART2 AT91CAP9_BASE_US2 /* + * SCKCR flags + */ +#define AT91CAP9_SCKCR_RCEN (1 << 0) /* RC Oscillator Enable */ +#define AT91CAP9_SCKCR_OSC32EN (1 << 1) /* 32kHz Oscillator Enable */ +#define AT91CAP9_SCKCR_OSC32BYP (1 << 2) /* 32kHz Oscillator Bypass */ +#define AT91CAP9_SCKCR_OSCSEL (1 << 3) /* Slow Clock Selector */ +#define AT91CAP9_SCKCR_OSCSEL_RC (0 << 3) +#define AT91CAP9_SCKCR_OSCSEL_32 (1 << 3) + +/* * Internal Memory. */ #define AT91CAP9_SRAM_BASE 0x00100000 /* Internal SRAM base address */ |