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authorJens Scharsig <js_at_ng@scharsoft.de>2010-02-03 22:46:01 +0100
committerTom Rix <Tom.Rix@windriver.com>2010-02-12 12:31:54 -0600
commit5d8e359c38d3ab80015e47d0cab792efe75cacf9 (patch)
treef849cd642eddfc10a66dd76d8e39ec01413b946b /include/asm-arm/arch-at91/at91sam9_sdramc.h
parent425de62d40f84524b90e776b141b060cd438a9fe (diff)
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add c structures for SoC access
* add's c structures for SoC access to pheriperials head files Signed-off-by: Jens Scharsig <js_at_ng@scharsoft.de>
Diffstat (limited to 'include/asm-arm/arch-at91/at91sam9_sdramc.h')
-rw-r--r--include/asm-arm/arch-at91/at91sam9_sdramc.h13
1 files changed, 13 insertions, 0 deletions
diff --git a/include/asm-arm/arch-at91/at91sam9_sdramc.h b/include/asm-arm/arch-at91/at91sam9_sdramc.h
index 5af2b54..c3da3a6 100644
--- a/include/asm-arm/arch-at91/at91sam9_sdramc.h
+++ b/include/asm-arm/arch-at91/at91sam9_sdramc.h
@@ -17,6 +17,19 @@
#ifndef AT91SAM9_SDRAMC_H
#define AT91SAM9_SDRAMC_H
+#ifdef __ASSEMBLY__
+
+#ifndef AT91_SDRAMC_BASE
+#define AT91_SDRAMC_BASE AT91_SDRAMC0_BASE
+#endif
+
+#define AT91_ASM_SDRAMC_MR AT91_SDRAMC_BASE
+#define AT91_ASM_SDRAMC_TR (AT91_SDRAMC_BASE + 0x04)
+#define AT91_ASM_SDRAMC_CR (AT91_SDRAMC_BASE + 0x08)
+#define AT91_ASM_SDRAMC_MDR (AT91_SDRAMC_BASE + 0x24)
+
+#endif
+
/* SDRAM Controller (SDRAMC) registers */
#define AT91_SDRAMC_MR (AT91_SDRAMC + 0x00) /* SDRAM Controller Mode Register */
#define AT91_SDRAMC_MODE (0xf << 0) /* Command Mode */