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| author | Peter Pearse <peter.pearse@arm.com> | 2007-11-09 15:24:26 +0000 |
|---|---|---|
| committer | Peter Pearse <peter.pearse@arm.com> | 2007-11-09 15:24:26 +0000 |
| commit | 5ca9881aad8c413ac2a82868a5e3719178254502 (patch) | |
| tree | d5146b7135702a3fa2833c99a2c3df4ab0f8cc63 /include/asm-arm/arch-arm1136 | |
| parent | 992742a5b09d9040adbd156fb90756af66ade310 (diff) | |
| download | u-boot-imx-5ca9881aad8c413ac2a82868a5e3719178254502.zip u-boot-imx-5ca9881aad8c413ac2a82868a5e3719178254502.tar.gz u-boot-imx-5ca9881aad8c413ac2a82868a5e3719178254502.tar.bz2 | |
Add apollon board support
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Diffstat (limited to 'include/asm-arm/arch-arm1136')
| -rw-r--r-- | include/asm-arm/arch-arm1136/mux.h | 2 | ||||
| -rw-r--r-- | include/asm-arm/arch-arm1136/omap2420.h | 33 |
2 files changed, 31 insertions, 4 deletions
diff --git a/include/asm-arm/arch-arm1136/mux.h b/include/asm-arm/arch-arm1136/mux.h index 67c8419..8bcd7a3 100644 --- a/include/asm-arm/arch-arm1136/mux.h +++ b/include/asm-arm/arch-arm1136/mux.h @@ -28,6 +28,7 @@ typedef unsigned int uint32; void muxSetupSDRC(void); void muxSetupGPMC(void); void muxSetupUsb0(void); +void muxSetupUsbHost(void); void muxSetupUart3(void); void muxSetupI2C1(void); void muxSetupUART1(void); @@ -70,6 +71,7 @@ void muxSetupHDQ(void); #define CONTROL_PADCONF_SPI1_SIMO ((volatile unsigned char *)0x48000100) #define CONTROL_PADCONF_SPI1_SOMI ((volatile unsigned char *)0x48000101) #define CONTROL_PADCONF_SPI1_NCS0 ((volatile unsigned char *)0x48000102) +#define CONTROL_PADCONF_SPI1_NCS1 ((volatile unsigned char *)0x48000103) #define CONTROL_PADCONF_MCBSP1_FSR ((volatile unsigned char *)0x4800010B) diff --git a/include/asm-arm/arch-arm1136/omap2420.h b/include/asm-arm/arch-arm1136/omap2420.h index d833035..0c11bec 100644 --- a/include/asm-arm/arch-arm1136/omap2420.h +++ b/include/asm-arm/arch-arm1136/omap2420.h @@ -77,6 +77,20 @@ #define GPMC_CONFIG5_1 (OMAP2420_GPMC_BASE+0xA0) #define GPMC_CONFIG6_1 (OMAP2420_GPMC_BASE+0xA4) #define GPMC_CONFIG7_1 (OMAP2420_GPMC_BASE+0xA8) +#define GPMC_CONFIG1_2 (OMAP2420_GPMC_BASE+0xC0) +#define GPMC_CONFIG2_2 (OMAP2420_GPMC_BASE+0xC4) +#define GPMC_CONFIG3_2 (OMAP2420_GPMC_BASE+0xC8) +#define GPMC_CONFIG4_2 (OMAP2420_GPMC_BASE+0xCC) +#define GPMC_CONFIG5_2 (OMAP2420_GPMC_BASE+0xD0) +#define GPMC_CONFIG6_2 (OMAP2420_GPMC_BASE+0xD4) +#define GPMC_CONFIG7_2 (OMAP2420_GPMC_BASE+0xD8) +#define GPMC_CONFIG1_3 (OMAP2420_GPMC_BASE+0xF0) +#define GPMC_CONFIG2_3 (OMAP2420_GPMC_BASE+0xF4) +#define GPMC_CONFIG3_3 (OMAP2420_GPMC_BASE+0xF8) +#define GPMC_CONFIG4_3 (OMAP2420_GPMC_BASE+0xFC) +#define GPMC_CONFIG5_3 (OMAP2420_GPMC_BASE+0x100) +#define GPMC_CONFIG6_3 (OMAP2420_GPMC_BASE+0x104) +#define GPMC_CONFIG7_3 (OMAP2420_GPMC_BASE+0x108) /* SMS */ #define OMAP2420_SMS_BASE 0x68008000 @@ -209,13 +223,24 @@ #define SRAM_OFFSET2 0x0000F800 #define SRAM_VECT_CODE (SRAM_OFFSET0|SRAM_OFFSET1|SRAM_OFFSET2) -#define LOW_LEVEL_SRAM_STACK 0x4020FFFC - -#define PERIFERAL_PORT_BASE 0x480FE003 - /* FPGA on Debug board.*/ #define ETH_CONTROL_REG (H4_CS1_BASE+0x30b) #define LAN_RESET_REGISTER (H4_CS1_BASE+0x1c) #endif /* endif CONFIG_2420H4 */ +#if defined(CONFIG_APOLLON) +#define APOLLON_CS0_BASE 0x00000000 /* OneNAND */ +#define APOLLON_CS1_BASE 0x08000000 /* ethernet */ +#define APOLLON_CS2_BASE 0x10000000 /* OneNAND */ +#define APOLLON_CS3_BASE 0x18000000 /* NOR */ + +#define ETH_CONTROL_REG (APOLLON_CS1_BASE + 0x30b) +#define LAN_RESET_REGISTER (APOLLON_CS1_BASE + 0x1c) +#endif /* endif CONFIG_APOLLON */ + +/* Common */ +#define LOW_LEVEL_SRAM_STACK 0x4020FFFC + +#define PERIFERAL_PORT_BASE 0x480FE003 + #endif |