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author | Wolfgang Denk <wd@denx.de> | 2008-01-09 11:30:15 +0100 |
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committer | Wolfgang Denk <wd@denx.de> | 2008-01-09 11:30:15 +0100 |
commit | 2eb6e01049886bdaadf11243e7c8cf674c34ed0b (patch) | |
tree | 01df3c1af8b933b6b313c21c258e637a990f835b /include/asm-arm/arch-arm1136/omap2420.h | |
parent | d2ba6bd8f431c51d8b381791091c133b1e6f8d02 (diff) | |
parent | 4985ca5af3767ffe13ea96e1dc26f88c81084414 (diff) | |
download | u-boot-imx-2eb6e01049886bdaadf11243e7c8cf674c34ed0b.zip u-boot-imx-2eb6e01049886bdaadf11243e7c8cf674c34ed0b.tar.gz u-boot-imx-2eb6e01049886bdaadf11243e7c8cf674c34ed0b.tar.bz2 |
Merge branch 'master' of git://www.denx.de/git/u-boot-arm
Diffstat (limited to 'include/asm-arm/arch-arm1136/omap2420.h')
-rw-r--r-- | include/asm-arm/arch-arm1136/omap2420.h | 33 |
1 files changed, 29 insertions, 4 deletions
diff --git a/include/asm-arm/arch-arm1136/omap2420.h b/include/asm-arm/arch-arm1136/omap2420.h index d833035..0c11bec 100644 --- a/include/asm-arm/arch-arm1136/omap2420.h +++ b/include/asm-arm/arch-arm1136/omap2420.h @@ -77,6 +77,20 @@ #define GPMC_CONFIG5_1 (OMAP2420_GPMC_BASE+0xA0) #define GPMC_CONFIG6_1 (OMAP2420_GPMC_BASE+0xA4) #define GPMC_CONFIG7_1 (OMAP2420_GPMC_BASE+0xA8) +#define GPMC_CONFIG1_2 (OMAP2420_GPMC_BASE+0xC0) +#define GPMC_CONFIG2_2 (OMAP2420_GPMC_BASE+0xC4) +#define GPMC_CONFIG3_2 (OMAP2420_GPMC_BASE+0xC8) +#define GPMC_CONFIG4_2 (OMAP2420_GPMC_BASE+0xCC) +#define GPMC_CONFIG5_2 (OMAP2420_GPMC_BASE+0xD0) +#define GPMC_CONFIG6_2 (OMAP2420_GPMC_BASE+0xD4) +#define GPMC_CONFIG7_2 (OMAP2420_GPMC_BASE+0xD8) +#define GPMC_CONFIG1_3 (OMAP2420_GPMC_BASE+0xF0) +#define GPMC_CONFIG2_3 (OMAP2420_GPMC_BASE+0xF4) +#define GPMC_CONFIG3_3 (OMAP2420_GPMC_BASE+0xF8) +#define GPMC_CONFIG4_3 (OMAP2420_GPMC_BASE+0xFC) +#define GPMC_CONFIG5_3 (OMAP2420_GPMC_BASE+0x100) +#define GPMC_CONFIG6_3 (OMAP2420_GPMC_BASE+0x104) +#define GPMC_CONFIG7_3 (OMAP2420_GPMC_BASE+0x108) /* SMS */ #define OMAP2420_SMS_BASE 0x68008000 @@ -209,13 +223,24 @@ #define SRAM_OFFSET2 0x0000F800 #define SRAM_VECT_CODE (SRAM_OFFSET0|SRAM_OFFSET1|SRAM_OFFSET2) -#define LOW_LEVEL_SRAM_STACK 0x4020FFFC - -#define PERIFERAL_PORT_BASE 0x480FE003 - /* FPGA on Debug board.*/ #define ETH_CONTROL_REG (H4_CS1_BASE+0x30b) #define LAN_RESET_REGISTER (H4_CS1_BASE+0x1c) #endif /* endif CONFIG_2420H4 */ +#if defined(CONFIG_APOLLON) +#define APOLLON_CS0_BASE 0x00000000 /* OneNAND */ +#define APOLLON_CS1_BASE 0x08000000 /* ethernet */ +#define APOLLON_CS2_BASE 0x10000000 /* OneNAND */ +#define APOLLON_CS3_BASE 0x18000000 /* NOR */ + +#define ETH_CONTROL_REG (APOLLON_CS1_BASE + 0x30b) +#define LAN_RESET_REGISTER (APOLLON_CS1_BASE + 0x1c) +#endif /* endif CONFIG_APOLLON */ + +/* Common */ +#define LOW_LEVEL_SRAM_STACK 0x4020FFFC + +#define PERIFERAL_PORT_BASE 0x480FE003 + #endif |