diff options
| author | Stefan Roese <sr@denx.de> | 2008-10-21 11:43:08 +0200 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2008-10-21 11:43:08 +0200 |
| commit | f61f1e150c84f5b9347fca79a4bc5f2286c545d2 (patch) | |
| tree | ab90f076f18e56b2b3e8c9375b95917daa78c1d9 /include/altera.h | |
| parent | ec081c2c190148b374e86a795fb6b1c49caeb549 (diff) | |
| parent | f82642e33899766892499b163e60560fbbf87773 (diff) | |
| download | u-boot-imx-f61f1e150c84f5b9347fca79a4bc5f2286c545d2.zip u-boot-imx-f61f1e150c84f5b9347fca79a4bc5f2286c545d2.tar.gz u-boot-imx-f61f1e150c84f5b9347fca79a4bc5f2286c545d2.tar.bz2 | |
Merge branch 'master' of /home/stefan/git/u-boot/u-boot
Diffstat (limited to 'include/altera.h')
| -rw-r--r-- | include/altera.h | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/include/altera.h b/include/altera.h index c03fe87..44a1ee5 100644 --- a/include/altera.h +++ b/include/altera.h @@ -29,19 +29,19 @@ /* Altera Model definitions *********************************************************************/ -#define CFG_ACEX1K CFG_FPGA_DEV( 0x1 ) -#define CFG_CYCLON2 CFG_FPGA_DEV( 0x2 ) -#define CFG_STRATIX_II CFG_FPGA_DEV( 0x4 ) +#define CONFIG_SYS_ACEX1K CONFIG_SYS_FPGA_DEV( 0x1 ) +#define CONFIG_SYS_CYCLON2 CONFIG_SYS_FPGA_DEV( 0x2 ) +#define CONFIG_SYS_STRATIX_II CONFIG_SYS_FPGA_DEV( 0x4 ) -#define CFG_ALTERA_ACEX1K (CFG_FPGA_ALTERA | CFG_ACEX1K) -#define CFG_ALTERA_CYCLON2 (CFG_FPGA_ALTERA | CFG_CYCLON2) -#define CFG_ALTERA_STRATIX_II (CFG_FPGA_ALTERA | CFG_STRATIX_II) +#define CONFIG_SYS_ALTERA_ACEX1K (CONFIG_SYS_FPGA_ALTERA | CONFIG_SYS_ACEX1K) +#define CONFIG_SYS_ALTERA_CYCLON2 (CONFIG_SYS_FPGA_ALTERA | CONFIG_SYS_CYCLON2) +#define CONFIG_SYS_ALTERA_STRATIX_II (CONFIG_SYS_FPGA_ALTERA | CONFIG_SYS_STRATIX_II) /* Add new models here */ /* Altera Interface definitions *********************************************************************/ -#define CFG_ALTERA_IF_PS CFG_FPGA_IF( 0x1 ) /* passive serial */ -#define CFG_ALTERA_IF_FPP CFG_FPGA_IF( 0x2 ) /* fast passive parallel */ +#define CONFIG_SYS_ALTERA_IF_PS CONFIG_SYS_FPGA_IF( 0x1 ) /* passive serial */ +#define CONFIG_SYS_ALTERA_IF_FPP CONFIG_SYS_FPGA_IF( 0x2 ) /* fast passive parallel */ /* Add new interfaces here */ typedef enum { /* typedef Altera_iface */ |