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author | Michal Simek <michal.simek@xilinx.com> | 2013-05-01 18:05:56 +0200 |
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committer | Michal Simek <michal.simek@xilinx.com> | 2013-05-06 10:41:30 +0200 |
commit | b03b25caea1ff3a501161f5bc1ad5e5b5b124e0c (patch) | |
tree | aa90d9289407d75f664b96cc614ba94ab84bb4a0 /include/altera.h | |
parent | 6631db4773cd735688bf3332173a49271df23385 (diff) | |
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fpga: Remove all CONFIG_SYS_* fpga related options
All these macros are completely unused by any code.
CONFIG_FPGA is not a bitfield anymore.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@ti.com>
Diffstat (limited to 'include/altera.h')
-rw-r--r-- | include/altera.h | 17 |
1 files changed, 0 insertions, 17 deletions
diff --git a/include/altera.h b/include/altera.h index 7a2bece..6aad5ee 100644 --- a/include/altera.h +++ b/include/altera.h @@ -27,23 +27,6 @@ #ifndef _ALTERA_H_ #define _ALTERA_H_ -/* Altera Model definitions - *********************************************************************/ -#define CONFIG_SYS_ACEX1K CONFIG_SYS_FPGA_DEV( 0x1 ) -#define CONFIG_SYS_CYCLON2 CONFIG_SYS_FPGA_DEV( 0x2 ) -#define CONFIG_SYS_STRATIX_II CONFIG_SYS_FPGA_DEV( 0x4 ) - -#define CONFIG_SYS_ALTERA_ACEX1K (CONFIG_SYS_FPGA_ALTERA | CONFIG_SYS_ACEX1K) -#define CONFIG_SYS_ALTERA_CYCLON2 (CONFIG_SYS_FPGA_ALTERA | CONFIG_SYS_CYCLON2) -#define CONFIG_SYS_ALTERA_STRATIX_II (CONFIG_SYS_FPGA_ALTERA | CONFIG_SYS_STRATIX_II) -/* Add new models here */ - -/* Altera Interface definitions - *********************************************************************/ -#define CONFIG_SYS_ALTERA_IF_PS CONFIG_SYS_FPGA_IF( 0x1 ) /* passive serial */ -#define CONFIG_SYS_ALTERA_IF_FPP CONFIG_SYS_FPGA_IF( 0x2 ) /* fast passive parallel */ -/* Add new interfaces here */ - typedef enum { /* typedef Altera_iface */ min_altera_iface_type, /* insert all new types after this */ passive_serial, /* serial data and external clock */ |