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author | Terry Lv <r65388@freescale.com> | 2010-05-12 22:49:24 +0800 |
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committer | Terry Lv <r65388@freescale.com> | 2010-06-24 16:54:31 +0800 |
commit | 90bfe6af18c84a7e3ba424cba0c2602d883bd286 (patch) | |
tree | 815e35b0cefc847806cef9a8df09bdad1c3955ad /include/ahci.h | |
parent | 6fa1a0ea0c589b327e8106d13ffff115d2553284 (diff) | |
download | u-boot-imx-90bfe6af18c84a7e3ba424cba0c2602d883bd286.zip u-boot-imx-90bfe6af18c84a7e3ba424cba0c2602d883bd286.tar.gz u-boot-imx-90bfe6af18c84a7e3ba424cba0c2602d883bd286.tar.bz2 |
ENGR00122651: Add dwc_ahsata support
Add dwc_ahsata support.
Signed-off-by: Terry Lv <r65388@freescale.com>
Diffstat (limited to 'include/ahci.h')
-rw-r--r-- | include/ahci.h | 14 |
1 files changed, 10 insertions, 4 deletions
diff --git a/include/ahci.h b/include/ahci.h index 0c6bbbd..12f653a 100644 --- a/include/ahci.h +++ b/include/ahci.h @@ -1,4 +1,7 @@ /* + * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. + * Terry Lv <r65388@freescale.com> + * * Copyright (C) Freescale Semiconductor, Inc. 2006. * Author: Jason Jin<Jason.jin@freescale.com> * Zhang Wei<wei.zhang@freescale.com> @@ -25,15 +28,18 @@ #ifndef _AHCI_H_ #define _AHCI_H_ +#include <pci.h> + #define AHCI_PCI_BAR 0x24 #define AHCI_MAX_SG 56 /* hardware max is 64K */ +#define AHCI_MAX_CMD_SLOT 32 #define AHCI_CMD_SLOT_SZ 32 #define AHCI_RX_FIS_SZ 256 #define AHCI_CMD_TBL_HDR 0x80 #define AHCI_CMD_TBL_CDB 0x40 -#define AHCI_CMD_TBL_SZ AHCI_CMD_TBL_HDR + (AHCI_MAX_SG * 16) -#define AHCI_PORT_PRIV_DMA_SZ AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_SZ \ - + AHCI_RX_FIS_SZ +#define AHCI_CMD_TBL_SZ (AHCI_CMD_TBL_HDR + (AHCI_MAX_SG * 16)) +#define AHCI_PORT_PRIV_DMA_SZ (AHCI_CMD_SLOT_SZ * AHCI_MAX_CMD_SLOT + \ + AHCI_CMD_TBL_SZ + AHCI_RX_FIS_SZ) #define AHCI_CMD_ATAPI (1 << 5) #define AHCI_CMD_WRITE (1 << 6) #define AHCI_CMD_PREFETCH (1 << 7) @@ -179,7 +185,7 @@ struct ahci_probe_ent { u32 host_flags; u32 host_set_flags; u32 mmio_base; - u32 pio_mask; + u32 pio_mask; u32 udma_mask; u32 flags; u32 cap; /* cache of HOST_CAP register */ |