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| author | Ye Li <ye.li@nxp.com> | 2016-10-11 17:20:58 +0800 |
|---|---|---|
| committer | Ye Li <ye.li@nxp.com> | 2016-10-13 16:34:21 +0800 |
| commit | 5ad998cbb8698052315d29bffaa4e264ebe4aad4 (patch) | |
| tree | 21141ee41068266e85e76e50107daf8b64d77a5b /fs | |
| parent | 18019b8f4b65d3261db6488e416eae66a6500316 (diff) | |
| download | u-boot-imx-5ad998cbb8698052315d29bffaa4e264ebe4aad4.zip u-boot-imx-5ad998cbb8698052315d29bffaa4e264ebe4aad4.tar.gz u-boot-imx-5ad998cbb8698052315d29bffaa4e264ebe4aad4.tar.bz2 | |
MLK-13336 mx6sll_arm2: Update LPDDR2 script to v2.1
Changes:
Version 2.1
-Issue a Precharge-All command prior to the MRW Reset command.
setmem /32 0x021B001C = 0x00008050 // [MMDC_MDSCR] precharge all to CS0
setmem /32 0x021B001C = 0x00008058 // [MMDC_MDSCR] precharge all to CS1
-Update MMDC PHY Read/Write delay-lines Configuration Register according to calibration results
setmem /32 0x021B0848 = 0x3A383C40 // [MMDC_MPRDDLCTL]
setmem /32 0x021B0850 = 0x242C3020 // [MMDC_MPWRDLCTL]
File:
http://compass.freescale.net/livelink/livelink?func=ll&objId=235701297&objAction=browse&viewType=1
Test:
Passed overnight memtester on one i.MX6SLL LPDDR2 ARM2 board.
Signed-off-by: Ye Li <ye.li@nxp.com>
Diffstat (limited to 'fs')
0 files changed, 0 insertions, 0 deletions