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| author | Poddar, Sourav <sourav.poddar@ti.com> | 2013-10-07 15:53:00 +0530 |
|---|---|---|
| committer | Jagannadha Sutradharudu Teki <jaganna@xilinx.com> | 2013-10-07 17:55:51 +0530 |
| commit | 62d206dc3126914f187cfb72e8a7c6cf84c19b7c (patch) | |
| tree | 509be84dae9d26378f38db6adc4bf11719ba9d1e /fs/yaffs2 | |
| parent | c97a9b3275997b09729aaf11bd8ace08478447a2 (diff) | |
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armv7: hw_data: change clock divider setting.
Clock requirement for qspi clk is 192 Mhz.
According to the below formulae,
f dpll = f ref * 2 * m /(n + 1)
clockoutx2_Hmn = f dpll / (hmn+ 1)
fref = 20 Mhz, m = 96, n = 4 gives f dpll = 768 Mhz
For clockoutx2_Hmn to be 768, hmn + 1 should be 4.
Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Diffstat (limited to 'fs/yaffs2')
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