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| author | York Sun <yorksun@freescale.com> | 2014-06-23 15:15:54 -0700 |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2014-07-03 08:40:51 +0200 |
| commit | 2f78eae5064728d6cd907148cfeaf8ba3e63b0ef (patch) | |
| tree | 80b5d23e3c6d46424909954cbc9504288e8f7156 /examples | |
| parent | 22932ffc03e521130cfd33cae1fc2531eb42604a (diff) | |
| download | u-boot-imx-2f78eae5064728d6cd907148cfeaf8ba3e63b0ef.zip u-boot-imx-2f78eae5064728d6cd907148cfeaf8ba3e63b0ef.tar.gz u-boot-imx-2f78eae5064728d6cd907148cfeaf8ba3e63b0ef.tar.bz2 | |
ARMv8/FSL_LSCH3: Add FSL_LSCH3 SoC
Freescale LayerScape with Chassis Generation 3 is a set of SoCs with
ARMv8 cores and 3rd generation of Chassis. We use different MMU setup
to support memory map and cache attribute for these SoCs. MMU and cache
are enabled very early to bootst performance, especially for early
development on emulators. After u-boot relocates to DDR, a new MMU
table with QBMan cache access is created in DDR. SMMU pagesize is set
in SMMU_sACR register. Both DDR3 and DDR4 are supported.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com>
Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
Diffstat (limited to 'examples')
0 files changed, 0 insertions, 0 deletions