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| author | Masahiro Yamada <yamada.m@jp.panasonic.com> | 2014-02-04 17:24:24 +0900 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2014-02-19 11:07:50 -0500 |
| commit | 9e4140329ee9a787d0f96ac2829d618d47f7973f (patch) | |
| tree | 6a40432f6f6723ba9ac5309076af17aec3bc0a9b /examples/standalone | |
| parent | d958002589cb724907e8d4360d546403d1e6b7d8 (diff) | |
| download | u-boot-imx-9e4140329ee9a787d0f96ac2829d618d47f7973f.zip u-boot-imx-9e4140329ee9a787d0f96ac2829d618d47f7973f.tar.gz u-boot-imx-9e4140329ee9a787d0f96ac2829d618d47f7973f.tar.bz2 | |
kbuild: change out-of-tree build
This commit changes the working directory
where the build process occurs.
Before this commit, build process occurred under the source
tree for both in-tree and out-of-tree build.
That's why we needed to add $(obj) prefix to all generated
files in makefiles like follows:
$(obj)u-boot.bin: $(obj)u-boot
Here, $(obj) is empty for in-tree build, whereas it points
to the output directory for out-of-tree build.
And our old build system changes the current working directory
with "make -C <sub-dir>" syntax when descending into the
sub-directories.
On the other hand, Kbuild uses a different idea
to handle out-of-tree build and directory descending.
The build process of Kbuild always occurs under the output tree.
When "O=dir/to/store/output/files" is given, the build system
changes the current working directory to that directory and
restarts the make.
Kbuild uses "make -f $(srctree)/scripts/Makefile.build obj=<sub-dir>"
syntax for descending into sub-directories.
(We can write it like "make $(obj)=<sub-dir>" with a shorthand.)
This means the current working directory is always the top
of the output directory.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Tested-by: Gerhard Sittig <gsi@denx.de>
Diffstat (limited to 'examples/standalone')
| -rw-r--r-- | examples/standalone/Makefile | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/examples/standalone/Makefile b/examples/standalone/Makefile index 1f8d70c..a6819f7 100644 --- a/examples/standalone/Makefile +++ b/examples/standalone/Makefile @@ -31,7 +31,7 @@ clean-files := $(extra-) $(addsuffix .srec,$(extra-)) $(addsuffix .bin,$(extra- COBJS := $(ELF:=.o) -LIB = $(obj)libstubs.o +LIB = $(obj)/libstubs.o LIBAOBJS-$(CONFIG_PPC) += ppc_longjmp.o ppc_setjmp.o LIBAOBJS-$(CONFIG_8xx) += test_burst_lib.o @@ -39,11 +39,11 @@ LIBAOBJS := $(LIBAOBJS-y) LIBCOBJS = stubs.o -LIBOBJS = $(addprefix $(obj),$(LIBAOBJS) $(LIBCOBJS)) +LIBOBJS = $(addprefix $(obj)/,$(LIBAOBJS) $(LIBCOBJS)) SRCS := $(COBJS:.o=.c) $(LIBCOBJS:.o=.c) $(LIBAOBJS:.o=.S) -OBJS := $(addprefix $(obj),$(COBJS)) -ELF := $(addprefix $(obj),$(ELF)) +OBJS := $(addprefix $(obj)/,$(COBJS)) +ELF := $(addprefix $(obj)/,$(ELF)) gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`) @@ -67,13 +67,13 @@ $(LIB): $(LIBOBJS) $(call cmd_link_o_target, $(LIBOBJS)) $(ELF): -$(obj)%: $(obj)%.o $(LIB) +$(obj)/%: $(obj)/%.o $(LIB) $(LD) $(LDFLAGS) -g -Ttext $(CONFIG_STANDALONE_LOAD_ADDR) \ -o $@ -e $(SYM_PREFIX)$(notdir $(<:.o=)) $< $(LIB) \ -L$(gcclibdir) -lgcc -$(obj)%.srec: $(obj)% +$(obj)/%.srec: $(obj)/% $(OBJCOPY) -O srec $< $@ 2>/dev/null -$(obj)%.bin: $(obj)% +$(obj)/%.bin: $(obj)/% $(OBJCOPY) -O binary $< $@ 2>/dev/null |