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| author | Marc Zyngier <marc.zyngier@arm.com> | 2014-07-12 14:23:59 +0100 |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2014-07-28 17:06:19 +0200 |
| commit | 800c83522ca6a7d6fd0b058f423501b4cc52d6d6 (patch) | |
| tree | a4865793a45efcb3552f5e9e5cc256ad7f4fab27 /dts | |
| parent | c19e0dd7412f5c4bce8c5057c40e747b1acb39e2 (diff) | |
| download | u-boot-imx-800c83522ca6a7d6fd0b058f423501b4cc52d6d6.zip u-boot-imx-800c83522ca6a7d6fd0b058f423501b4cc52d6d6.tar.gz u-boot-imx-800c83522ca6a7d6fd0b058f423501b4cc52d6d6.tar.bz2 | |
ARM: HYP/non-sec: add a barrier after setting SCR.NS==1
A CP15 instruction execution can be reordered, requiring an
isb to be sure it is executed in program order.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Diffstat (limited to 'dts')
0 files changed, 0 insertions, 0 deletions