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authorFabio Estevam <fabio.estevam@freescale.com>2015-06-25 17:06:17 -0300
committerPeng Fan <Peng.Fan@freescale.com>2015-06-29 21:41:29 +0800
commitf75fba3a63f23ef980a98c4072f38d71fbd6fdba (patch)
tree50779325d1d6efc37cce4dcb3c964c2d0d890e35 /dts
parent71c6ce1e85eb57888a87527df6b04ccf07c0c641 (diff)
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MLK-11201 mx7: clock: Fix PLL divider for the 100MHz case
We should divide the 1000MHz ENET PLL clock by 10 in order to achieve 100MHz, so fix the divider accordingly. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
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