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authorWolfgang Denk <wd@denx.de>2009-10-27 20:56:31 +0100
committerWolfgang Denk <wd@denx.de>2009-10-27 20:56:31 +0100
commit98cecb610f3fa53aa7d825a634d35ef9cf6c5487 (patch)
treef9a153be5ec31919981e4d53e5ee274cffa3d15b /drivers
parenta747a7f31059b9069e97c78bba5496409c33aa05 (diff)
parent3fca80375981fe83d4674a0267183b469a1ea7ff (diff)
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Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
Diffstat (limited to 'drivers')
-rw-r--r--drivers/pci/fsl_pci_init.c18
-rw-r--r--drivers/qe/fdt.c2
2 files changed, 18 insertions, 2 deletions
diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c
index 87944bf..8fbab68 100644
--- a/drivers/pci/fsl_pci_init.c
+++ b/drivers/pci/fsl_pci_init.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2007 Freescale Semiconductor, Inc.
+ * Copyright 2007-2009 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
@@ -413,13 +413,27 @@ void fsl_pci_init(struct pci_controller *hose, u32 cfg_addr, u32 cfg_data)
}
int fsl_pci_init_port(struct fsl_pci_info *pci_info,
- struct pci_controller *hose, int busno)
+ struct pci_controller *hose, int busno, int pcie_ep)
{
volatile ccsr_fsl_pci_t *pci;
struct pci_region *r;
pci = (ccsr_fsl_pci_t *) pci_info->regs;
+ if (pcie_ep) {
+ volatile pit_t *pi = &pci->pit[2];
+
+ pci_setup_indirect(hose, (u32)&pci->cfg_addr,
+ (u32)&pci->cfg_data);
+ out_be32(&pi->pitar, 0);
+ out_be32(&pi->piwbar, 0);
+ out_be32(&pi->piwar, PIWAR_EN | PIWAR_LOCAL |
+ PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP | PIWAR_IWS_4K);
+
+ fsl_pci_config_unlock(hose);
+ return 0;
+ }
+
/* on non-PCIe controllers we don't have pme_msg_det so this code
* should do nothing since the read will return 0
*/
diff --git a/drivers/qe/fdt.c b/drivers/qe/fdt.c
index 5307488..d7c7d13 100644
--- a/drivers/qe/fdt.c
+++ b/drivers/qe/fdt.c
@@ -85,6 +85,8 @@ void ft_qe_setup(void *blob)
"bus-frequency", gd->qe_clk, 1);
do_fixup_by_compat_u32(blob, "fsl,qe",
"brg-frequency", gd->brg_clk, 1);
+ do_fixup_by_compat_u32(blob, "fsl,qe-gtm",
+ "clock-frequency", gd->qe_clk / 2, 1);
fdt_fixup_qe_firmware(blob);
#endif
}