Merge branch 'master' of git://git.denx.de/u-boot-arm

Conflicts:
	arch/arm/include/asm/mach-types.h
	common/serial.c

Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

14 files changed, 163 insertions, 13 deletions

diff --git a/drivers/block/fsl_sata.c b/drivers/block/fsl_sata.c
index abcda6f..8878560 100644
--- a/drivers/block/fsl_sata.c
+++ b/drivers/block/fsl_sata.c
@@ -21,6 +21,7 @@
 #include <common.h>
 #include <command.h>
 #include <asm/io.h>
+#include <asm/processor.h>
 #include <malloc.h>
 #include <libata.h>
 #include <fis.h>
@@ -191,6 +192,27 @@ int init_sata(int dev)
 	/* Wait the controller offline */
 	ata_wait_register(&reg->hstatus, HSTATUS_ONOFF, 0, 1000);
 
+#if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001)
+	/*
+	 * For P1022/1013 Rev1.0 silicon, after power on SATA host
+	 * controller is configured in legacy mode instead of the
+	 * expected enterprise mode. software needs to clear bit[28]
+	 * of HControl register to change to enterprise mode from
+	 * legacy mode.
+	 */
+	{
+		u32 svr = get_svr();
+		if (IS_SVR_REV(svr, 1, 0) &&
+		    ((SVR_SOC_VER(svr) == SVR_P1022) ||
+		     (SVR_SOC_VER(svr) == SVR_P1022_E) ||
+		     (SVR_SOC_VER(svr) == SVR_P1013) ||
+		     (SVR_SOC_VER(svr) == SVR_P1013_E))) {
+			out_le32(&reg->hstatus, 0x20000000);
+			out_le32(&reg->hcontrol, 0x00000100);
+		}
+	}
+#endif
+
 	/* Set the command header base address to CHBA register to tell DMA */
 	out_le32(&reg->chba, (u32)cmd_hdr & ~0x3);
 
diff --git a/drivers/block/fsl_sata.h b/drivers/block/fsl_sata.h
index 18e88fa..576efaf 100644
--- a/drivers/block/fsl_sata.h
+++ b/drivers/block/fsl_sata.h
@@ -243,8 +243,12 @@ typedef struct prd_entry {
 
 /* ext_c_ddc
 */
-#define PRD_ENTRY_EXT		0x80000000 /* extension flag or called indirect descriptor flag */
-#define PRD_ENTRY_DATA_SNOOP	0x00400000 /* Snoop enable for all data associated with the PRD entry */
+#define PRD_ENTRY_EXT		0x80000000 /* extension flag */
+#ifdef CONFIG_FSL_SATA_V2
+#define PRD_ENTRY_DATA_SNOOP	0x10000000 /* Data snoop enable */
+#else
+#define PRD_ENTRY_DATA_SNOOP	0x00400000 /* Data snoop enable */
+#endif
 #define PRD_ENTRY_LEN_MASK	0x003fffff /* Data word count */
 
 #define PRD_ENTRY_MAX_XFER_SZ	(PRD_ENTRY_LEN_MASK + 1)
diff --git a/drivers/i2c/fsl_i2c.c b/drivers/i2c/fsl_i2c.c
index 2241990..cb13dee 100644
--- a/drivers/i2c/fsl_i2c.c
+++ b/drivers/i2c/fsl_i2c.c
@@ -221,9 +221,10 @@ i2c_init(int speed, int slaveadd)
 	unsigned int temp;
 
 #ifdef CONFIG_SYS_I2C_INIT_BOARD
-	/* call board specific i2c bus reset routine before accessing the   */
-	/* environment, which might be in a chip on that bus. For details   */
-	/* about this problem see doc/I2C_Edge_Conditions.                  */
+	/* Call board specific i2c bus reset routine before accessing the
+	 * environment, which might be in a chip on that bus. For details
+	 * about this problem see doc/I2C_Edge_Conditions.
+	*/
 	i2c_init_board();
 #endif
 	dev = (struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_I2C_OFFSET);
@@ -249,6 +250,15 @@ i2c_init(int speed, int slaveadd)
 	writeb(0x0, &dev->sr);			/* clear status register */
 	writeb(I2C_CR_MEN, &dev->cr);		/* start I2C controller */
 #endif
+
+#ifdef CONFIG_SYS_I2C_BOARD_LATE_INIT
+	/* Call board specific i2c bus reset routine AFTER the bus has been
+	 * initialized. Use either this callpoint or i2c_init_board;
+	 * which is called before i2c_init operations.
+	 * For details about this problem see doc/I2C_Edge_Conditions.
+	*/
+	i2c_board_late_init();
+#endif
 }
 
 static int
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 0f6f8b1..a9b07a9 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -72,8 +72,10 @@ uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
 	uint xfertyp = 0;
 
 	if (data) {
-		xfertyp |= XFERTYP_DPSEL | XFERTYP_DMAEN;
-
+		xfertyp |= XFERTYP_DPSEL;
+#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
+		xfertyp |= XFERTYP_DMAEN;
+#endif
 		if (data->blocks > 1) {
 			xfertyp |= XFERTYP_MSBSEL;
 			xfertyp |= XFERTYP_BCEN;
@@ -97,6 +99,71 @@ uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
 	return XFERTYP_CMD(cmd->cmdidx) | xfertyp;
 }
 
+#ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
+/*
+ * PIO Read/Write Mode reduce the performace as DMA is not used in this mode.
+ */
+static int
+esdhc_pio_read_write(struct mmc *mmc, struct mmc_data *data)
+{
+	struct fsl_esdhc *regs = mmc->priv;
+	uint blocks;
+	char *buffer;
+	uint databuf;
+	uint size;
+	uint irqstat;
+	uint timeout;
+
+	if (data->flags & MMC_DATA_READ) {
+		blocks = data->blocks;
+		buffer = data->dest;
+		while (blocks) {
+			timeout = PIO_TIMEOUT;
+			size = data->blocksize;
+			irqstat = esdhc_read32(&regs->irqstat);
+			while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_BREN)
+				&& --timeout);
+			if (timeout <= 0) {
+				printf("\nData Read Failed in PIO Mode.");
+				return timeout;
+			}
+			while (size && (!(irqstat & IRQSTAT_TC))) {
+				udelay(100); /* Wait before last byte transfer complete */
+				irqstat = esdhc_read32(&regs->irqstat);
+				databuf = in_le32(&regs->datport);
+				*((uint *)buffer) = databuf;
+				buffer += 4;
+				size -= 4;
+			}
+			blocks--;
+		}
+	} else {
+		blocks = data->blocks;
+		buffer = data->src;
+		while (blocks) {
+			timeout = PIO_TIMEOUT;
+			size = data->blocksize;
+			irqstat = esdhc_read32(&regs->irqstat);
+			while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_BWEN)
+				&& --timeout);
+			if (timeout <= 0) {
+				printf("\nData Write Failed in PIO Mode.");
+				return timeout;
+			}
+			while (size && (!(irqstat & IRQSTAT_TC))) {
+				udelay(100); /* Wait before last byte transfer complete */
+				databuf = *((uint *)buffer);
+				buffer += 4;
+				size -= 4;
+				irqstat = esdhc_read32(&regs->irqstat);
+				out_le32(&regs->datport, databuf);
+			}
+			blocks--;
+		}
+	}
+}
+#endif
+
 static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
 {
 	uint wml_value;
@@ -104,6 +171,17 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
 	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 	struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
 
+#ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
+	if (!(data->flags & MMC_DATA_READ)) {
+		if ((esdhc_read32(&regs->prsstat) & PRSSTAT_WPSPL) == 0) {
+			printf("\nThe SD card is locked. "
+				"Can not write to a locked card.\n\n");
+			return TIMEOUT;
+		}
+		esdhc_write32(&regs->dsaddr, (u32)data->src);
+	} else
+		esdhc_write32(&regs->dsaddr, (u32)data->dest);
+#else
 	wml_value = data->blocksize/4;
 
 	if (data->flags & MMC_DATA_READ) {
@@ -124,6 +202,7 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
 					wml_value << 16);
 		esdhc_write32(&regs->dsaddr, (u32)data->src);
 	}
+#endif
 
 	esdhc_write32(&regs->blkattr, data->blocks << 16 | data->blocksize);
 
@@ -220,6 +299,9 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
 
 	/* Wait until all of the blocks are transferred */
 	if (data) {
+#ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
+		esdhc_pio_read_write(mmc, data);
+#else
 		do {
 			irqstat = esdhc_read32(&regs->irqstat);
 
@@ -230,6 +312,7 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
 				return TIMEOUT;
 		} while (!(irqstat & IRQSTAT_TC) &&
 				(esdhc_read32(&regs->prsstat) & PRSSTAT_DLA));
+#endif
 	}
 
 	esdhc_write32(&regs->irqstat, -1);
diff --git a/drivers/pci/pci_auto.c b/drivers/pci/pci_auto.c
index 82e4eed..87ee2c2 100644
--- a/drivers/pci/pci_auto.c
+++ b/drivers/pci/pci_auto.c
@@ -1,5 +1,5 @@
 /*
- * arch/ppc/kernel/pci_auto.c
+ * arch/powerpc/kernel/pci_auto.c
  *
  * PCI autoconfiguration library
  *
diff --git a/drivers/qe/uec_phy.c b/drivers/qe/uec_phy.c
index c1cc23b..fa48fea 100644
--- a/drivers/qe/uec_phy.c
+++ b/drivers/qe/uec_phy.c
@@ -47,7 +47,7 @@
 /*--------------------------------------------------------------------+
  * Fixed PHY (PHY-less) support for Ethernet Ports.
  *
- * Copied from arch/ppc/cpu/ppc4xx/4xx_enet.c
+ * Copied from arch/powerpc/cpu/ppc4xx/4xx_enet.c
  *--------------------------------------------------------------------*/
 
 /*
diff --git a/drivers/serial/altera_jtag_uart.c b/drivers/serial/altera_jtag_uart.c
index fb28aa9..2980e4d 100644
--- a/drivers/serial/altera_jtag_uart.c
+++ b/drivers/serial/altera_jtag_uart.c
@@ -38,8 +38,16 @@ int serial_init( void ) { return(0);}
 
 void serial_putc (char c)
 {
-	while (NIOS_JTAG_WSPACE ( readl (&jtag->control)) == 0)
-		WATCHDOG_RESET ();
+	while (1) {
+		unsigned st = readl(&jtag->control);
+		if (NIOS_JTAG_WSPACE(st))
+			break;
+#ifdef CONFIG_ALTERA_JTAG_UART_BYPASS
+		if (!(st & NIOS_JTAG_AC)) /* no connection */
+			return;
+#endif
+		WATCHDOG_RESET();
+	}
 	writel ((unsigned char)c, &jtag->data);
 }
 
diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
index b3bf10b..23c0f76 100644
--- a/drivers/serial/ns16550.c
+++ b/drivers/serial/ns16550.c
@@ -1,6 +1,6 @@
 /*
  * COM1 NS16550 support
- * originally from linux source (arch/ppc/boot/ns16550.c)
+ * originally from linux source (arch/powerpc/boot/ns16550.c)
  * modified to use CONFIG_SYS_ISA_MEM and new defines
  */
 
diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c
index dd5f332..8eda95c 100644
--- a/drivers/serial/serial.c
+++ b/drivers/serial/serial.c
@@ -115,6 +115,7 @@ static NS16550_t serial_ports[4] = {
 	name,\
 	bus,\
 	eserial##port##_init,\
+	NULL,\
 	eserial##port##_setbrg,\
 	eserial##port##_getc,\
 	eserial##port##_tstc,\
diff --git a/drivers/serial/serial_pxa.c b/drivers/serial/serial_pxa.c
index 9ba457e..b74e439 100644
--- a/drivers/serial/serial_pxa.c
+++ b/drivers/serial/serial_pxa.c
@@ -266,6 +266,7 @@ struct serial_device serial_ffuart_device =
 	"serial_ffuart",
 	"PXA",
 	ffuart_init,
+	NULL,
 	ffuart_setbrg,
 	ffuart_getc,
 	ffuart_tstc,
@@ -310,6 +311,7 @@ struct serial_device serial_btuart_device =
 	"serial_btuart",
 	"PXA",
 	btuart_init,
+	NULL,
 	btuart_setbrg,
 	btuart_getc,
 	btuart_tstc,
@@ -354,6 +356,7 @@ struct serial_device serial_stuart_device =
 	"serial_stuart",
 	"PXA",
 	stuart_init,
+	NULL,
 	stuart_setbrg,
 	stuart_getc,
 	stuart_tstc,
diff --git a/drivers/serial/serial_s3c24x0.c b/drivers/serial/serial_s3c24x0.c
index 5dd4dd8..8a3e302 100644
--- a/drivers/serial/serial_s3c24x0.c
+++ b/drivers/serial/serial_s3c24x0.c
@@ -78,6 +78,7 @@ DECLARE_GLOBAL_DATA_PTR;
 	name, \
 	bus, \
 	s3serial##port##_init, \
+	NULL,\
 	s3serial##port##_setbrg, \
 	s3serial##port##_getc, \
 	s3serial##port##_tstc, \
diff --git a/drivers/serial/serial_s5p.c b/drivers/serial/serial_s5p.c
index 68b8d01..9747db3 100644
--- a/drivers/serial/serial_s5p.c
+++ b/drivers/serial/serial_s5p.c
@@ -185,6 +185,7 @@ void s5p_serial##port##_puts(const char *s) { serial_puts_dev(s, port); }
 	name, \
 	bus, \
 	s5p_serial##port##_init, \
+	NULL, \
 	s5p_serial##port##_setbrg, \
 	s5p_serial##port##_getc, \
 	s5p_serial##port##_tstc, \
diff --git a/drivers/spi/mpc8xxx_spi.c b/drivers/spi/mpc8xxx_spi.c
index 687ffe6..44ab39d 100644
--- a/drivers/spi/mpc8xxx_spi.c
+++ b/drivers/spi/mpc8xxx_spi.c
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2006 Ben Warren, Qstreams Networks Inc.
- * With help from the common/soft_spi and arch/ppc/cpu/mpc8260 drivers
+ * With help from the common/soft_spi and arch/powerpc/cpu/mpc8260 drivers
  *
  * See file CREDITS for list of people who contributed to this
  * project.
diff --git a/drivers/video/mx3fb.c b/drivers/video/mx3fb.c
index 1e1d507..99a595e 100644
--- a/drivers/video/mx3fb.c
+++ b/drivers/video/mx3fb.c
@@ -56,6 +56,7 @@ void lcd_panel_disable(void)
 
 #define msleep(a) udelay(a * 1000)
 
+#ifndef CONFIG_DISPLAY_VBEST_VGG322403
 #define XRES		240
 #define YRES		320
 #define PANEL_TYPE	IPU_PANEL_TFT
@@ -70,6 +71,22 @@ void lcd_panel_disable(void)
 #define SIG_POL		(DI_D3_DRDY_SHARP_POL | DI_D3_CLK_POL)
 #define IF_CONF		0
 #define IF_CLK_DIV	0x175
+#else /* Display Vbest VGG322403 */
+#define XRES		320
+#define YRES		240
+#define PANEL_TYPE	IPU_PANEL_TFT
+#define PIXEL_CLK	156000
+#define PIXEL_FMT	IPU_PIX_FMT_RGB666
+#define H_START_WIDTH	20		/* left_margin */
+#define H_SYNC_WIDTH	30		/* hsync_len */
+#define H_END_WIDTH	(38 + 30)	/* right_margin + hsync_len */
+#define V_START_WIDTH	7		/* upper_margin */
+#define V_SYNC_WIDTH	3		/* vsync_len */
+#define V_END_WIDTH	(26 + 3)	/* lower_margin + vsync_len */
+#define SIG_POL		(DI_D3_DRDY_SHARP_POL | DI_D3_CLK_POL)
+#define IF_CONF		0
+#define IF_CLK_DIV	0x175
+#endif
 
 #define LCD_COLOR_IPU	LCD_COLOR16