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| author | Jerry Huang <Chang-Ming.Huang@freescale.com> | 2010-11-25 17:06:07 +0000 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2010-12-18 23:15:21 +0100 |
| commit | 4a6ee172c3e6e8419e2e61d345a2c993016bb781 (patch) | |
| tree | bdf362cd1f84f9fc8b7fdc289def3c05ae0308a3 /drivers | |
| parent | 73c65e0e77cb5005cc4fa2c0cb435f1dffb90a71 (diff) | |
| download | u-boot-imx-4a6ee172c3e6e8419e2e61d345a2c993016bb781.zip u-boot-imx-4a6ee172c3e6e8419e2e61d345a2c993016bb781.tar.gz u-boot-imx-4a6ee172c3e6e8419e2e61d345a2c993016bb781.tar.bz2 | |
fsl_esdhc: Use mmc_set_clock to set initial speed
After booting the u-boot, and first using some SD card (such as Sandisk 2G SD
card), because the field 'clock' of struct mmc is zero, this will cause
the read transfer is always active and SDHC DATA line is always active,
therefore, driver can't handle the next command.
Therefore, we use mmc_set_clock to setup both the data structure and HW
to the initial clock speed of 400000Hz.
Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com>
Tested-by: Stefano Babic <sbabic@denx.de>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/mmc/fsl_esdhc.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 57cd4ee..73d5cd3 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -398,7 +398,7 @@ static int esdhc_init(struct mmc *mmc) esdhc_write32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN); /* Set the initial clock speed */ - set_sysctl(mmc, 400000); + mmc_set_clock(mmc, 400000); /* Disable the BRR and BWR bits in IRQSTAT */ esdhc_clrbits32(®s->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR); |