diff options
| author | Wolfgang Denk <wd@pollux.denx.de> | 2006-03-12 18:06:37 +0100 |
|---|---|---|
| committer | Wolfgang Denk <wd@pollux.denx.de> | 2006-03-12 18:06:37 +0100 |
| commit | d8169c9f3ba04f5e470008c59afa3161ce683524 (patch) | |
| tree | 0ae4af4bd36beea39691ac5e65a1bc1744282eae /drivers | |
| parent | 0a3471fc780c1a38496c3b99c443ffe3edca4b56 (diff) | |
| download | u-boot-imx-d8169c9f3ba04f5e470008c59afa3161ce683524.zip u-boot-imx-d8169c9f3ba04f5e470008c59afa3161ce683524.tar.gz u-boot-imx-d8169c9f3ba04f5e470008c59afa3161ce683524.tar.bz2 | |
Fix bad register definitions for LTX971 PHY on MPC85xx boards.
Patch by Gerhard Jaeger, 21 Jun 2005
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/tsec.h | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/drivers/tsec.h b/drivers/tsec.h index c26fcc0..e3bbff0 100644 --- a/drivers/tsec.h +++ b/drivers/tsec.h @@ -161,12 +161,12 @@ #define MIIM_DM9161_10BTCSR_INIT 0x7800 /* LXT971 Status 2 registers */ -#define MIIM_LXT971_SR2 17 /* Status Register 2 */ -#define MIIM_LXT971_SR2_SPEED_MASK 0xf000 -#define MIIM_LXT971_SR2_10HDX 0x1000 /* 10 Mbit half duplex selected */ -#define MIIM_LXT971_SR2_10FDX 0x2000 /* 10 Mbit full duplex selected */ -#define MIIM_LXT971_SR2_100HDX 0x4000 /* 100 Mbit half duplex selected */ -#define MIIM_LXT971_SR2_100FDX 0x8000 /* 100 Mbit full duplex selected */ +#define MIIM_LXT971_SR2 0x11 /* Status Register 2 */ +#define MIIM_LXT971_SR2_SPEED_MASK 0x4200 +#define MIIM_LXT971_SR2_10HDX 0x0000 /* 10 Mbit half duplex selected */ +#define MIIM_LXT971_SR2_10FDX 0x0200 /* 10 Mbit full duplex selected */ +#define MIIM_LXT971_SR2_100HDX 0x4000 /* 100 Mbit half duplex selected */ +#define MIIM_LXT971_SR2_100FDX 0x4200 /* 100 Mbit full duplex selected */ #define MIIM_READ_COMMAND 0x00000001 |