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| author | Vivek Mahajan <vivek.mahajan@freescale.com> | 2009-10-27 12:18:55 +0530 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2009-10-27 09:33:51 -0500 |
| commit | 70ed869ea5f6b1d13d7b140c83ec0dcd8a127ddc (patch) | |
| tree | 25395b163b80a1acae7f69b9a515f110d9bdf364 /drivers | |
| parent | 273a28ad9ef59dcfcd4c056ec1f61f1e0896cfaa (diff) | |
| download | u-boot-imx-70ed869ea5f6b1d13d7b140c83ec0dcd8a127ddc.zip u-boot-imx-70ed869ea5f6b1d13d7b140c83ec0dcd8a127ddc.tar.gz u-boot-imx-70ed869ea5f6b1d13d7b140c83ec0dcd8a127ddc.tar.bz2 | |
ppc/85xx/pci: fsl_pci_init: pcie agent mode support
Originally written by Jason Jin and Mingkai Hu for mpc8536.
When QorIQ based board is configured as a PCIe agent, then unlock/enable
inbound PCI configuration cycles and init a 4K inbound memory window;
so that a PCIe host can access the PCIe agents SDRAM at address 0x0
* Supported in fsl_pci_init_port() after adding pcie_ep as a param
* Revamped copyright in drivers/pci/fsl_pci_init.c
* Mods in 85xx based board specific pci init after this change
Signed-off-by: Vivek Mahajan <vivek.mahajan@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/pci/fsl_pci_init.c | 18 |
1 files changed, 16 insertions, 2 deletions
diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c index 87944bf..8fbab68 100644 --- a/drivers/pci/fsl_pci_init.c +++ b/drivers/pci/fsl_pci_init.c @@ -1,5 +1,5 @@ /* - * Copyright 2007 Freescale Semiconductor, Inc. + * Copyright 2007-2009 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -413,13 +413,27 @@ void fsl_pci_init(struct pci_controller *hose, u32 cfg_addr, u32 cfg_data) } int fsl_pci_init_port(struct fsl_pci_info *pci_info, - struct pci_controller *hose, int busno) + struct pci_controller *hose, int busno, int pcie_ep) { volatile ccsr_fsl_pci_t *pci; struct pci_region *r; pci = (ccsr_fsl_pci_t *) pci_info->regs; + if (pcie_ep) { + volatile pit_t *pi = &pci->pit[2]; + + pci_setup_indirect(hose, (u32)&pci->cfg_addr, + (u32)&pci->cfg_data); + out_be32(&pi->pitar, 0); + out_be32(&pi->piwbar, 0); + out_be32(&pi->piwar, PIWAR_EN | PIWAR_LOCAL | + PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP | PIWAR_IWS_4K); + + fsl_pci_config_unlock(hose); + return 0; + } + /* on non-PCIe controllers we don't have pme_msg_det so this code * should do nothing since the read will return 0 */ |